A wideband blocker-resilient direct delta sigma receiver with selective input-impedance matching

This paper presents a wideband blocker-tolerant direct ΔΣ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\varDelta \varSigma$$\end{document} receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. In addition, with the help of reduced gain design, near band blocker gain is minimized, further improving the blocker resilience. The receiver is designed for configurable operation from 0.7–2.7 GHz and a baseband bandwidth of 10 MHz. Simulated in a 28 nm technology, the DDSR demonstrates a maximum noise figure of 6.2 dB, and achieves a peak SNDR of 53 dB with an out-of-band 1 dB input compression point of -11\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$-\,11$$\end{document} dBm at a 100 MHz offset.


Introduction
Wireless receivers for emerging radio access standards such as 5G and LTE-A demand a reconfigurable operation on multiple frequency bands and across a wireless spectrum of several GHz. To meet this required reconfigurability, several digital intensive architectures have been envisioned [1][2][3][4]. Among these, one showing promising performance is the direct-DR-receiver (DDSR). The architecture was first presented in [5] and investigated further in [6][7][8][9][10].
The wideband DDSR architecture differs from conventional direct conversion receivers by embedding RF frontend units as part of a delta-sigma-modulator (DSM) loop-filter. As shown in Fig. 1, the DDSR brings the outermost loop of the feedback type DR modulator to the output of a low noise amplifier (LNA). In this way, signal discretization already begins at RF and the DSM loop filter performs the functions of both baseband filtering and quantization noise shaping.
Inherently, such wideband receivers are exposed to high power out-of-band (OB) blockers. If not attenuated, these blockers may completely saturate the receiver and make reception non-linear. Traditionally, OB blocker resilience has been achieved by utilizing external off-chip filtering. However, as external filters are generally non-tunable and bulky, multiple filters are required to cover wide range of receiver bands. Two widely used on-chip alternatives for improving blocker resilience in wideband receivers are: (1) applying N-path filtering at the LNA output and (2) lownoise transconductance amplifier/mixer first arrangements [2,6,9,[11][12][13][14][15][16]. However, as will be explained later, these techniques have certain blocker rejection limitations such as not addressing the OB linearity degradation due to receiver input transconductor swing range limitation.
In this paper we propose a blocker resilient DDSR which attenuates blockers at both the input and output nodes of LNA. The additional bandpass filtering at LNA input is achieved through design of a low-intrinsic input impedance LNA, which provides OB voltage attenuation when driven by source impedance higher than LNA input impedance. On the other hand, at the desired signal frequency, input impedance is boosted to matched condition by implementation of positive upconverted feedback from the DDSR output. Additionally, we follow an approach of reduced receiver gain design which results in an improved near-band compression point. Evaluated with detailed simulations in a 28 nm technology, the proposed selective input impedance matching and reduced gain design approach demonstrates state-of-the art blocker tolerance, when compared with recently published DDSRs.
The paper is organized as follows. Section 2 describes the limitations of blocker rejection with basic N-path filtering and how rejection can be improved with our proposed solution of selective input impedance and reduced gain design. Section 3 details the design method for the proposed DDSR while Sect. 4 covers its transistor level implementation details. We finalize the discussion with performance evaluation results in Sect. 5 and conclusions in Sect. 6.

Blocker rejection at the DDSR input
In DDSRs blocker rejection is usually achieved by implementing N-path filtering technique at the LNA output [5,6]. However, there are two limitations with this approach. First, the gain/loss of far-away blockers is limited by the N-path mixer switch resistance (R SW ) and the LNA transconductance (g m,LNA ) which should both be minimized. These parameters cannot be reduced indefinitely due to limitations on local oscillator (LO) drive power consumption and LNA noise contribution. Second, filtering is implemented only at LNA output, neglecting the filtering requirement at the input. Without input filtering and provided the low blocker gain at the LNA output due to filtering, the LNA transconductor input swing range limits can reach earlier then its output. Therefore, an optimum design should ideally filter the OB blockers already at the LNA input.
In order to provide on-chip bandpass filtering at the DDSR input, the input impedance (R IN ) needs to be frequency dependent and lower than source impedance (R S ). The relative blocker voltage attenuation is proportional to the ratio between R S and R IN at blocker frequencies. Such an input impedance profile has been demonstrated earlier in [17,18] for LNA-first receivers and in [19] for mixer-first receivers. However, in both LNA-first and mixer-first designs, the selected input impedance profile was chosen to reduce the noise contribution of the front-end. The authors did not report the possibility of blocker attenuation through optimizing the input impedance profile. In this paper, we utilize this impedance profile to provide additional blocker voltage attenuation already at the DDSR input.

Blocker rejection through optimized gain design
In a typical down-conversion receiver, gain is needed for two reasons: First, it suppresses noise contributions from the later stages of the receiver. From this point of view, implementing gain more than the minimum required to suppress the noise contribution of later stages does not bring any benefit from noise perspective. Second, gain is needed so that the weakest input signal appearing at the analog-to-digital converter (ADC) input is sufficiently greater than the quantization noise of the ADC. For DDSRs, however, this ADC input range requirement is different and needs further explanation. Figure 2 presents a comparison of the typical output spectrum for a Nyquist-rate ADC based receiver and that of a DDSR. Typically, a Nyquist-rate ADC for a receiver is designed to meet certain signal-to-noise and distortion ratio (SNDR) requirement dictated by the communication standard. The maximum SNDR achieved by the ADC is limited on upper side by full-scale linear voltage swing range (V FS ) and on the lower side by the noise floor. A typical ADC design process starts from V FS and the required SNDR is achieved by pushing the ADC's quantization noise floor down by increasing the ADC resolution. After defining this resolution, sufficient gain needs to be applied in the receiver chain so that the amplified receiver thermal noise level at the ADC input is higher than the quantization noise floor. This ensures that the quantization noise does not contribute significantly to the overall receiver noise. Analytically we can calculate the minimum gain (G) requirement for Nyquist-ADC based receivers as: where P FS is the ADC full-scale power in dBm, SNR tar is the required SNR for a given specification, SNR min is the Fig. 1 Generic block diagram of the direct DR receiver. The RF stages are included in the DR modulator (DSM) loop-filter, thus minimizing the number of stages in the receiver minimum acceptable SNR for an acceptable reception, and f BW is the required channel bandwidth. In contrast, the DDSR design begins from the in-band thermal noise floor level at the input of the receiver. The amount of gain that is applied in the in the DDSR is selected solely based on what is needed to ensure that the LNA is the most significant noise contributor. The resolution of the quantizer and the loop filter order are then designed so that the in-band quantization noise is sufficiently lower than the amplified thermal noise. This ensures that the minimum amount of gain is applied in the receiver. Now let us consider how the lower gain helps to achieve optimized blocker rejection in DDSR design. High power blockers can make the receiver operation non-linear if they are strong enough to reach the swing range limitations of the designed RF and BB amplifiers. Any additional gain for blockers will result in amplifier swing range limitations being reached earlier. Therefore, whenever gain is applied in the receiver, it should be selective so that only desired signals are amplified and blockers are attenuated. Usually this is done in receivers through RF and/or BB filtering. However, filtering profiles for a single stage are generally limited to first-order roll-off after the cut-off frequency.
This means that any near-band blockers will not be suppressed adequately by a single filtering stage. A higher number of filtering stages with partitioned gain can be employed for reasonable suppression of near-band blocker signals. However, after a certain limit, increasing the number of stages becomes impractical due to increased power consumption. Another way to solve this problem is to implement higher-order filtering schemes such as in [15]. However, higher-order filtering still provides limited near-band blocker attenuation. Considering this limited roll-off of RF and BB filters, we propose to suppress the near-band blocker signals with minimum possible gain. This is easy to achieve in DDSRs, as the absolute power of DSM quantization noise is much lower than thermal noise floor due to the inherent noise shaping of DDSR.
Based on the aforementioned discussion, our proposed DDSR consists of optimized receiver gain design together with tunable bandpass filtering at the RF input. We now detail the design of proposed the DDSR. Figure 3 shows the block diagram of the proposed DDSR. In comparison to the traditional DDSR architecture, the proposed architecture differs in the front-end design. We intentionally design the intrinsic input impedance (R INT ) of the front-end to be lower than the antenna source impedance (R S ) while at the desired frequency this R INT is boosted to matched conditions by the application of upconverted positive feedback from the DDSR output (Fig. 5). As explained earlier, lower R IN at blocker frequencies helps to reduce blocker voltage gain already at the DDSR input.

DDSR design
Apart from attenuating the blockers from selective impedance profile, the proposed DDSR is designed with only the minimum closed loop gain (A CL ) required to suppress the noise contribution of later stages. The A CL gain is defined from the LNA input to DDSR output including the input impedance mismatch effects. As explained earlier, this reduced gain helps to achieve better near-band blocker rejection. An A CL of 20 dB is selected in this case which will suppress the noise contribution from later stages to about 10 Â. This means that later DDSR stages can be designed with much lower current. For such a case, combined noise factor (F tot ) of stages after the LNA can be derived as: here A CL should be put on linear scale, and F RX is the target NF of receiver. To achieve such F tot , we can approximate the later stage minimum required transconductance as: where g is process and channle-length dependent constant. After the selection of A CL , and referring to Fig. 4 for parameter definitions, the DDSR design is split into four steps: (1) the value of the positive feedback factor (b req ) and the DDSR open loop gain without the positive feedback (A OL ) are solved which provide the desired impedance match and A CL . (2) The loop-filter is designed with the calculated A OL specification. (3) we take into account the non-idealities of the N-path filter and demonstrate how the DSM coefficients are implemented in the circuit. Finally, in (4) positive feedback is implemented with a value of required feedback factor (b req ) from step one that matches R IN to R S and raises A OL to A CL (Fig. 5). In the

Positive feedback loop design
The purpose of the positive feedback loop in the proposed DDSR is to boost R IN to matched conditions. The loop consists of an upconverting passive mixer in series with resistance (R POS ). The digital BB output of the DDSR can be fed to the upconverting passive mixers either through a current-steering digital to analog converter (IDAC) or a low output-impedance voltage-mode DAC. In the following text we provide the design procedure with both IDAC and DAC implementations.

Case-I, DAC implementation
As explained, the positive feedback loop boosts R IN to matched conditions. However, the implementation of positive feedback also increases the gain of the DDSR and consequently reduces the bandwidth. Therefore, the initial open loop gain of DDSR without positive feedback (A OL ) should be designed to be lower than target A CL = 20 dB.
In order to find the starting A OL and the required value of positive feedback factor b req that gives the matched input impedance and A CL = 20 dB, the small-single model presented in Fig. 4 can be used. The presented model does not consider passive mixer upconversion losses, therefore, some deviation of analytical results from simulated response is expected. Nevertheless, for quadrature passive mixers with 25% duty-cycle, the difference is not large and results can be used with reasonable accuracy. For the presented model, a simple shunt-shunt positive feedback analysis with DAC gain (G DAC ) of unity provides [20]: where R INT is the intrinsic input impedance of the DDSR front-end and R DES is the desired R IN for a matched case.
In addition, A CL should be put on linear scale in all derived equations of the presented model. Provided that the calculated b req is lower than the maximum theoretical b req \1=A OL , a stable implementation of b req is possible. The positive feedback factor b can be implemented by design as: where R SW is the passive mixer switch resistance and r o is the output impedance of DAC. This means that b req can be achieved by controlling the value of R POS in the positive feedback loop. Based on b req , we can calculate the starting open-loop gain A OL that will result in A CL = 20 dB after the implementation of positive feedback.
where the calculated A OL is in linear scale. As a design example we select R INT = 15 X, R DES = 50 X, G ADC = 1 and R S = 50 X. These values are extracted from the implemented circuits in DDSR and represent what can be practically be achieved. For example, reducing R INT to be lower than 15 X will increase the power consumption of LNA substantially. Based on the chosen parameters, the required feedback factor from Eq. ?? is b req % 0:005. In other words, R POS ?R SW ?r o of 200 X is required. Based on the calculated b req , Eq. 4 suggests A OL = 13.3 dB.

Case-II, IDAC implementation
As presented in Fig. 4, the IDAC implementation in the positive feedback path can be modeled with a voltage controlled current source having a transconductance g m,IDAC and output resistance r o . Following a simple shuntshunt feedback analysis, we can solve the value of positive feedback factor b that gives the required input impedance match and closed loop gain A CL .
Provided that b req is lower than the maximum theoretical b req \1=A OL , a stable implementation of b req is possible. The positive feedback factor b can be implemented by design as: This means that the required value of feedback factor can be achieved by controlling g m,IDAC and R POS (Fig. 4). Based on b req , we can calculate the starting open-loop gain A OL that will result in A CL = 20 dB after the implementation of positive feedback as:

Loop-filter design
Based on the calculated value of A OL , the next step is to design the DDSR loop-filter. As has been focus of the discussion, blockers are the main concern when designing a DDSR. Thus, it is also natural that we emphasize the signal transfer function (STF) in the loop-filter design. The cascade of integrators in feedback topology (CIFB) is well suited for a DDSR thanks to its well-defined and nonpeaking STF. The poles of the low-pass STF and high-pass noise transfer function (NTF) are identical, meaning that we can choose to design either the STF or NTF, which then fixes the other. We choose to design the STF, while keeping in mind the requirements for quantization noise shaping. Gain needs to be applied in the first stage, so that the noise performance requirement of the later stages can be relaxed. Based on the previous section, we select A OL = 13.3 dB gain in this case. For the out-of-band, we want to keep the applied gain to a minimum and therefore the first pole of the STF needs to be at channel bandwidth (f BW ).
Next, we need to calculate the number of additional noise shaping stages after the LNA required for fulfilling the quantization noise shaping requirement. The number of these stages can be calculated to be [6]: where D is the quantizer step size, f S is the sampling frequency, k is Boltzmann constant, T is the temperature in Kelvins (T = 300 K is used), A CL is the required receiver power gain after the implementation of positive feedback, F RX is the noise factor of the receiver excluding quantization noise, f BW is BB bandwidth cutoff frequency, and f NSP is the combined noise shaping pole cutoff frequency.
The closed loop gain of the receiver was targeted to be A CL = 20 dB, while the parameters D, F RX , f s and f NSP still remain undefined. In order to keep the focus of the paper on the positive feedback, we utilize an ideal 4-bit quantization and feedback with a clock delay added to emulate the required time for buffering and transistor switching. The differential input range for the quantizer is selected to be 600 mV, so that it is not the limiting factor for receiver linearity and thus we can calculate that D = 40 mV. Noise factor F RX is set by the device noise of amplifiers and the mixers, dominated by the noise of the first amplifier in the chain. For calculating the number of noise shaping stages, we use NF = 5 dB i.e. F RX = 3.1623, which is based on steadystate AC simulations when the discrete feedback is replaced by ideal continuous-time feedback.
The selection of the sampling frequency f s is critical in a DDSR. This is because the loop-filter contains mixers, that need to operate across the receiver frequency range. If no additional filtering is implemented for the feedback signal that is fed to the mixer nodes, LO frequencies that are not multiples of f s /2 will cause the quantization noise to fold to the in-band and potentially desensitize the receiver [5]. The severity of this effect is dependent on the absolute level of the quantization noise at LO frequency and its harmonics. In order to avoid this issue, we have locked the f s to LO frequency (f LO ). The f s will thus vary between 0.7-2.7 GHz.
A parameter that still remains undefined is the combined noise shaping pole cutoff frequency f NSP . In addition to being the key factor in determining the required number of stages, f NSP also affects the stability of the loop. The lower limit for f NSP is f BW as the number of stages increases to infinity. As a first order analysis, we can reason that the upper limit is f s /4, as the quantization noise removed from below this frequency has to fit between f s /4 and f s /2, leading to the stability criteria of 3 dB out-of-band gain for the NTF. As we approach the upper limit, the high-frequency gain of the NTF increases [21]. A high NTF gain will decrease feedback loop resilience against non-idealities, such as the excess-loop delay or clock jitter [22]. To navigate this trade-off, we select f NSP to be 10 times f BW , or 100 MHz, which is 1/7-1/27 of the f s .
Calculating the number of noise shaping stages from Eq. 10 with the chosen parameters gives n = 2.44-2.73 i.e. 3 stages. The resulting loop filter has a total of four stages where the first one provides gain and filtering and the following three ensure that the inband quantization noise is shaped below the thermal noise level. Next, the loop-filter coefficients need to be determined. Implementing an A OL = 13.3 dB and the chosen bandwidth requires that when normalized to f BW , a 1 ¼ 9:25 and b 1 ¼ 1. In order to avoid peaking, Butterworth coefficients are used in the noise shaping stages. The initial coefficients of the noise shaping stages are first normalized to f BW and then scaled so that a k ¼ G k b k , where G k is the gain of respective DSM filter stage. This results in dynamic range scaling, setting the dc gain of each noise shaping stage to unity. The initial and the scaled coefficients are listed in Table 1.
Based on above calculated coefficients, the STF of the proposed DDSR can be derived as: where H I is the integrator transfer function. For an ideal integrator it is 1/s. Figure 3 shows the block diagram of the proposed DDSR. The first integration stage consists of the LNA, downconverting passive mixers and integration capacitances at the baseband, which form an N-path filter. The second, third and fourth stage are implemented as g m C integrators. The noise performance of each stage is dependent on their transconductance g m , and thus the LNA and the g m stages are designed first. The LNA performance sets the noise figure to be roughly 5 dB, while the later stages are designed so that their contribution is minimal. Based on the designed g m of the stages, we can calculate the capacitances C 1-4 of the DSM loop filter and the feedback transconductances g m, fb,1-4 as [10,23]:

Loop filter implementation
R SH ¼ X 1 n¼3;7;11:: n¼5;9;13:: where R LNA is the output impedance of LNA, R BB is the parallel combination of C 1 impedance and input impedance of first BB amplifier, G 2-4 is the gain of respective DSM stages, h RF is the transfer function from the LNA input to the first BB output, h fb is the transfer function for the negative DSM feedback from DDSR output to first BB input and R SH represents the virtual shunt impedance representing the power dissipation due to baseband signal upconversion.
The final values of the circuit parameters are provided in Table 2.

Positive feedback implementation
Finally, positive feedback is implemented across the designed DDSR loop-filter. The required feedback factor b req is implemented by selecting a proper value for g m,IDAC and R POS . The resulting closed loop gain is equal to the required A CL = 20 dB and the input matched. However, the implementation of positive feedback reduces the bandwidth of the proposed DDSR. In order to circumvent the problem, the N-path capacitance C 1 needs to be scaled with a scaling factor of A OL /A CL to match the desired bandwidth. The final value of C 1 can be found as: where A OL and A CL are open and closed-loop gains on linear scale. Based on the system model and design equations presented earlier, Fig. 6 plots the required analytical transfer function for the proposed receiver.

System implementation
The DDSR is designed for an receiver gain of 20 dB. The RF front-end consists of a transconductor implementation with a parallel combination of common-gate CG and pushpull common-source CS amplifiers [16]. A common-gate amplifier is a valid choice as he input impedance can be easily controlled through common-gate transconductance. Figure 7(a) shows the circuit diagram of the designed transconductor. The parallel CG and CS combination increases the transconductor gain, and the push-pull configuration helps to achieve better large signal linearity. To maximize output voltage swing range of the transconductor, the output common-mode voltage is set to half of the supply voltage by implementing a common-mode feedback loop. Blocker filtering at the transconductor input is achieved by designing a low intrinsic input impedance (R INT ) of the transconductor while for desired frequency R INT is boosted to match source impedance (R S ) through implementation of up-converted positive feedback from the baseband (BB) output.
Ideally, the intrinsic input impedance of the LNA should be 0 X. However, due to practical limitations of LNA transconductor power consumption, differential intrinsic input impedance is designed to be 30 X. This intrinsic impedance is then boosted to matched condition by the positive feedback from the DDSR output to RF nodes through passive quadrature mixers. The amount of positive feedback can be controlled through positive feedback IDAC's transconductance g m,IDAC and series resistance R POS . Based on the analytical derivations from previous sections, we choose a g m,IDAC = 5.3 mS. As implementation of positive feedback is prone to instability, process corner simulations were carried out, for the chosen g m,IDAC , to ensure the stability of the system in all process corners.
Downconversion mixers in the main signal path were implemented as quadrature passive mixers driven with 25% duty cycle LO waveforms. Transistors with a large aspect-ratio of 48/0:03lm are implemented in the main path downconversion mixers. This ensured a small switch resistance of 8 X for better attenuation at far away offsets from f LO . As there was no such requirement of smaller R SW for the positive feedback mixers, their aspect ratio was selected to be four times smaller than main path mixers (12/0:03lm i.e. R SW = 32 X).
The later integrators were implemented with consecutively higher noise contribution. This is because once the gain is implemented in the system, later stages noise contribution is reduced by the amount of added gain. Therefore, there is no need for the later stage noise contribution to be low. Figure 7(b) shows the implemented dynamically-biased BB transonductors. All baseband amplifiers are designed with the same configuration as shown in Fig. 7(b) with the small exception of designing the first baseband transconductor with a transconductance of 23 mS and bias current of 3.8 mA. This is about 10 Â higher the the bias currents of later baseband stages to ensure reduced noise contribution from the first baseband amplifier. Capacitors C 1 -C 4 implement the required BB bandwidth bandwidth cutoff frequency (f BW ) and noise shaping pole cutoff frequency (f NSP ) in the DSM loop filter. Their values were selected based on the calculations from the previous section and are provided in Table 2.
The quantizer and feedback DACs were implemented as behavioral models. Nevertheless, the most important nonidealities of quantizer and feedback DAC such as clockdelay between DAC and quantizer and noise of DAC transistors were added to closely match the simulated behavior with real circuits.

Performance evaluation
The proposed DDSR was evaluated in a 28 nm fully-depleted silicon-on-insulator (FD-SOI) process through transient and steady-state AC simulations. The DDSR is reconfigurable from 0.7-2.7 GHz with a f BW of 10 MHz. Further, based on our previous implementation [6], we added estimated values I/O pad capacitances, bondwire inductances, s-parameter models of 20 nH off-chip RFchokes, and clock delay between the quantizer and IDACs in order to match the simulated results more closely to the real scenario.
The spectrum of the DDSR output bit stream for an input signal and blocker power of À 43 dBm is shown in Fig. 8. A few key points can be observed. First, the desired in-band signal is amplified with about A CL = 20 dB of receiver gain. Second, the blocker at 73 MHz offset from f LO is filtered by the baseband filtering response, and third, the quantization noise is shaped by the DDSR feedback loop such that the in-band quantization noise is lower than thermal noise floor. Figure 9 shows the simulated steady-state AC analysis results of DDSR gain and S 11 . As desired, A CL = 20 dB is observed within the 20 MHz RF bandwidth. Further, a differential out-of-band input impedance of 30 X can be seen needed for blocker attenuation at LNA input. Figures 10 show the receiver SNDR versus input signal and blocker powers. the receiver achieves a maximum SNDR of 53 dB at P IN of À 43 dBm. Further, we observe a decrease in SNDR from at blocker input powers greater than À 35 dBm for an input signal power of À 80 dBm. At low signal powers, the difference between ideal and simulated SNDRs is approximately equal to receiver NF.   Figure 11 presents a comparison of the simulated SNDR for cases when f S = 1.5 GHz and f S = f LO . It can be seen that for a constant f S = 1.5 GHz, SNDR degrades from its maximum value for f LO 6 ¼ nf S /2, here n is an integer number. This degradation occurs due to the quantization noise upconversion effect inherent in DDSR architectures [5]. However, in the proposed structure, the degradation of SNDR due to quantization noise upconversion is much more severe than in a traditional DDSR. This is due to bringing the DDSR feedback to the input of receiver rather than to the LNA output. As there is no preceding gain stage before this input, the upconverted quantization noise effect is more severe on achieved SNDR. The problem was solved in the final design by choosing f LO = f S for the entire band of operation. As can be seen in Fig. 11, this ensures that the degradation of SNDR due to quantization noise upconversion effects is minimal. Figure 12 presents the SNDR versus clock delay for two different sampling frequencies of f S = 0.7 GHz and 1.5 GHz. The clock delay is defined from the rising edge f S to the instant when output of IDAC begins to change. It can be seen that the DDSR loop is able to handle about 70 ps of delay, in the worst case f S = 0.7 GHz, before the SNDR begins to degrade rapidly. At higher sampling frequencies, DSM loop is able to handle much longer delays than 70 ps. This is because a higher sampling frequency brings the response more close to a continuous time filter with more resilience towards clock delay. While the delay of 70 ps is still implementable in the given process, the process variations can increase the delay to be higher than 70 ps. Therefore, a better solution for worst case scenario of f S = 0.7 GHz will be to lock f S = 2f LO . Locking f S = 2f LO for the worst case scenario minimizes SNDR degradation due to quantization noise upconversion.
In addition to clock delay, the supply noise can also affect the maximum SNDR of the receiver.   shows the performance of receiver SNDR under the presence of supply noise. Figures 14 and 15 show the simulated NF, receiver gain and blocker input compression point (BCP). The receiver achieves a BCP of -11.5 dBm at 100 MHz offset from f LO with a maximum integrated receiver NF of 6.2 dB. When compared with BCP results collected into Table 3, the proposed approach is able to promising blocker tolerance even with its lower supply voltage.

Conclusion
We have proposed a blocker resilient DDSR with a low intrinsic input impedance front-end. It reduces blocker gain already at the LNA input by creating an on-chip tunable bandpass response. Furthermore, we proposed a reduced receiver gain design that helps to minimize near-band blocker gain. This ensures that the voltage swing limits are pushed towards much stronger blockers. The simulated results demonstrate an OB blocker compression point of -11.5 dBm and OB-IIP3 of 0 dBm at 100 MHz offset from the desired received frequency, with a maximum SNDR of 53 dB and a maximum NF of 6.2 dB. The results collected into Table 3 indicate that the proposed approach is able to achieve state-of-the art blocker tolerance even with its lower supply voltage.