Multiple soft fault diagnosis of DC analog CMOS circuits designed in nanometer technology

This paper is devoted to local multiple soft fault diagnosis of nonlinear DC analog CMOS circuits designed in nanometer technology. An algorithm is developed that allows estimating the values of a set of potentially faulty process parameters. It exploits two tests with the input nodes accessible for excitation and the output node accessible for measurement. One of the tests is used to find the parameter values. It leads to a system of nonlinear algebraic type equations that are not given in explicit analytical form and may be satisfied by several sets of the parameter values. To solve the system of the equations the Nelder–Mead optimization method is applied with the objective function properly modified during the computation process. Next the obtained solution, being a set of the parameter values, is validated using the other test. If the solution passes this test it is considered as the actual one. Otherwise, another solution is calculated and verified using the same approach. The developed diagnostic procedure has been implemented in DELPHI, whereas the required by the algorithm circuit analyses are performed using IsSPICE 4 and both environments have been joined together. For illustration three numerical examples are given.


Introduction
Fault diagnosis of analog circuits is an important problem in the design and testing of electronic devices . Generally, fault diagnosis includes detecting faulty circuits, locating faulty parameters and evaluating their values. If a faulty parameter is drifted from its tolerance range but does not lead to some topological changes, the fault is said to be soft or parametric. If a fault is open circuit or short circuit, it is called hard or catastrophic. In integrated circuits physical imperfections, such as near-opens or near-shorts may occur as spot defects [7,10,21,22]. The methods dedicated to soft fault diagnosis usually exploit the simulation after test approach, where circuit simulations take place after any testing. They are based on measurements of the voltages at accessible points of the circuit, leading to equations with the tested parameters as unknown variables.
In current CMOS technology the global variations of parameters are measured by dedicated test structures included in the wafer. However, the problem is how to identify the random local variations of the process parameters. The local variations are due to fabrication or due to aging phenomenon. They affect the components across the die independently. Examples of local variations in ICs include local geometrical deformations, such as variations in the channel length and width, the oxide thickness, etc.
Many concepts and methods focused on parametric fault diagnosis are presented in references [1-3, 5, 9, 11, 13, 16-20]. Most of the works, dealing with soft fault diagnosis of analog circuits, address only the case when just one parameter is faulty. Fewer papers are devoted to the multiple fault diagnosis, where several parameters can be faulty. In real circuits the test equations, that express the measured voltages in terms of the parameters are nonlinear and cannot be presented in explicit analytical form. These equations may actually have multiple solutions, which means that several sets of the parameter values meet the test. To find the multiple solutions the parametric homotopy [17], the simplicial homotopy [18], or the block relaxation method [19] were proposed. To determine the actual solution a new efficient approach was proposed in Ref. [20] as follows. Two tests of the circuit are arranged, one used to find the solutions and the other to check if the obtained solution is the actual one. To compute the solution the extended systematic search method was developed [20]. In this paper the Nelder-Mead optimization method is applied with the objective function properly modified during the computation process and similarly as in [20] the obtained result is checked using the validation test. If the obtained solution passes this test the algorithm terminates, otherwise another solution is calculated and verified. The procedure is carried out as long as the solution which meets the validation test is obtained.

Diagnostic tests
Let us consider a nonlinear DC circuit, with n parameters x 1 ; . . .; x n considered as potentially faulty, having one or more input nodes accessible for excitation and one output node accessible for measurement. We connect to the output node a resistor R o and apply DC voltage sources to the input nodes (see Fig. 1 (1) can be rewritten in the compact form The first test leading to Eq. (2) will be named a principal test (PT), whereas the second one will be named a validation test (VT). Unfortunately, in real electronic circuits the function g x ð Þ cannot be presented in explicit analytical form. However, the values ofg i x ð Þ i ¼ 1; . . .; n, for given x, can be found by performing the analyses of the circuits driven by the sources as in the test, with the parameters being the elements of vector x.

Fault diagnosis algorithm
An algorithm that allows finding actual values of the parameters x 1 ; . . .; x n is developed in this section. The algorithm solves the PT Eq. (2) and verifies the obtained solutions applying the VT. Its core is the Nelder-Mead optimization method [23][24][25]. The algorithm takes into consideration the possibility of existing several solutions of the nonlinear Eq. (2). Each of the solutions is a set of the parameters that meet the PT.
Since the algorithm exploits the Nelder-Mead method, a background of this method as well as the version that is used in this paper is described below. The Nelder-Mead method is designed to solve the unconstrained optimization problem of minimizing given nonlinear function f x ð Þ : R n ! R. In this paper the method is adapted to solve Eq. (2). For this purpose the function is formed, where a 1 ; . . .; a n are coefficients equal to zero or one. If all the coefficients are equal to one the function f x ð Þ will be called a complete function, otherwise a reduced function. The complete function is identical to the Euclidean norm of g x ð Þ, i.e., f x ð Þ ¼ g x ð Þ k k 2 . The Nelder-Mead method uses only the function values at some points in R n and does not require gradients at the points. This is why this method is very useful to solve Eq. (2), with g x ð Þ not given in explicit analytical form. The Nelder-Mead method is simplex-based [23][24][25]. An msimplex is a figure formed by m þ 1 independent points, The method exploits simplices having n þ 1 vertices S ¼ x 0 ; . . .; x n È É . The corresponding function values at these vertices are labeled f 0 ¼ f x 0 ð Þ; . . .; f n ¼ f x n ð Þ. At any stage of the computation process the method generates a new simplex, aimed at decreasing the function values at its vertices. To construct this simplex one or more new points are searched comparing their function values with those at the vertices. Generally the method terminates when the simplex becomes sufficiently small, or the simplex is flat or degenerated [24]. The crucial point of the Nelder-Mead method is creating an adjusted simplex to the current simplex S. In this paper the approach described in [23] is adopted. Choose the indices h, s, l, of the worst, second worst, and the best vertex of S so that f h ¼ max Fig. 3).
If f l f r \f s choose x r as the new vertex of the adjusted simplex. Otherwise, continue the procedure depending on whether f r \f l or f r ! f s .
If f e \f r choose x e as the new vertex, otherwise, choose x r as a new vertex.
-If f r ! f s , compute a point x c using the following approach.
If f c f r , choose x c as the vertex, otherwise, perform a shrink operation as described below.
If f c f h , choose x c as the vertex. Otherwise, perform a shrink operation.

Note
The coefficients c, b, d are chosen as proposed in Ref. [25]: As the initial simplex we choose the regular one using the procedure described in Ref. [24].
It should be emphasized that the function f x ð Þ is not given in explicit analytical form. In consequence, to find the value of the complete function f x ð Þ at given x, n analyses of the circuit must be performed applying the sources as in PT. This is time consuming process. The time is shrunk if f x ð Þ is the reduced function. Since the Nelder-Mead method requires large number of the values of f x ð Þ at various points x, the reduced function is exploited at some stages of the algorithm proposed in this paper. Moreover, for different reduced functions the method searches for the solution (a set of the parameters) in different directions. This observation is used to find a new solution, when the obtained one does not pass the VT. 3. Create the reduced function f x ð Þ specified by Eq. (3) with a 1 ¼ Á Á Á ¼ a nÀ1 ¼ 1, a n ¼ 0 and apply the Nelder-Mead method. If during the process a simplex is obtained so that the value of f x ð Þ at the best vertex is \100e 2 , the computation process is modified as follows. The obtained x is considered as an approximate solution. Next the complete function f x ð Þ is created by setting a 1 ¼ Á Á Á ¼ a n ¼ 1, a new regular simplex is constructed around this best vertex and the procedure is continued. If during the process a vertex, at which the value of f x ð Þ is less than e 1 appears, the parameters x 1 ; . . .; x n corresponding to this vertex meet the PT. Otherwise, go to Step 5. 4. Check if the obtained parameters satisfy the VT. For this purpose analyse the circuit with these parameters, driven by the sources as in VT, find the voltages ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi r 2 1 þ Á Á Á þ r 2 n p e 2 , the parameters are the actual ones. In such a case the algorithm terminates. Otherwise, they are virtual and we proceed to Step 5. 5. Modify the function f x ð Þ by setting a nÀ1 ¼ 0, a 1 ¼ Á Á Á ¼ a nÀ2 ¼ a n ¼ 1 and repeat the steps 3-4 adapted to this case.
This procedure can be continued if the actual parameters have not been found, by setting in succession a nÀ2 ¼ 0; Á Á Á ; a 1 ¼ 0. In any case the remaining coefficients are equal to one and the number of the generated simplices cannot exceed maximum value M.

Note
If at any stage of the algorithm the small or the flat simplex [24] appears, the set of the coefficients a 1 ; . . .; a n is changed as described in step 5. If the degenerated simplex [24] appears, a new regular simplex is created around the best vertex of this simplex and the process is continued.

Numerical examples
The proposed algorithm has been implemented in the joined environments: DELPHI and IsSPICE 4, and tested numerically using MOS circuits designed in nanometer technology. The calculations were executed on PC with the processor Intel Core (TM) i7-2600. To illustrate effectiveness of the algorithm we consider three exemplary circuits designed in nanometer technology.  On the basis of sensitivity analyses and numerical experiments the following sets of the values of V S 1 and V S 2 have been chosen to perform of the PT and VT.
All the four sets are exploited to test the parameters of the four NMOS transistors M4, M5, M8, M9 and the first three of them are used to test the parameters of the three PMOS transistors M1, M2, M3.
The results of different multiple soft fault diagnoses are summarized in Tables 1, 2 (Table 1), and in PMOS transistors M1, M2, M3 (Table 2), three sets of the simultaneous variations of all the oxide thicknesses in NMOS transistors M4, M5, M8, M9 (Table 3) and in PMOS transistors M1, M2, M3 (Table 4). In all the cases the obtained values of the parameters are very close to their actual values.
In this example the transistors M6 and M7 cannot be tested, because their parameters have very slight influence on the output voltage. Numerical experiments show that even in some idealized circumstances, under very high accuracy of the measurements of V o , equal to 0.01 lV, and M ¼ 5000 some determined parameters of these transistors can be erroneous and the CPU time long. Some exemplary results conforming this statement are included in Table 5. Figure 6 shows the CMOS circuit, being the voltage reference, designed in nanometer technology [27]. The measurement accuracy and the constants of the computation  Fig. 7 A rail-to-rail input buffer

Example 2
The results of various multiple soft fault diagnoses are summarized in Tables 6,7,8,9. They comprise three sets of the simultaneous variations of all the channel lengths in NMOS transistors (Table 6), in PMOS transistors (Table 7), and three sets of the simultaneous variations of all the oxide thicknesses in NMOS transistors (Table 8) and the PMOS transistors (Table 9). In all the cases the obtained values of the parameters are very close to their actual values.

Example 3
Let us consider the rail-to-rail input buffer [27] shown in Fig. 7. To arrange the diagnostic tests the input voltages V S 1 , V S 2 and V S 3 as well as the output voltage V o are selected. The constants of the computation process are the same as in Example 1, R o ¼ 100 kX. Sensitivity analyses of the output voltage due to variations of the parameters L and TOX of the transistors reveal that all the transistors can be tested.
The following sets of the values of the input voltages have been chosen.   Some results of multiple soft fault diagnosis are summarized in Tables 10, 11. The obtained values of the parameters are very close to their actual values.

Conclusion
The method developed in this paper allows effective diagnosing multiple soft faults of the process parameters in small and middle-size ICs designed in nanometer technology. The method does not require access to internal nodes of the circuit. The set of the parameter values is obtained by solving nonlinear equations, not given in explicit analytical form, that may have more than one solution. The proposed approach, whose core is the Nelder-Mead optimization method, is capable of finding the multiple solutions and select the actual one. Numerical examples reveal that the accuracy of the determined parameter values is very good. The method does not allow testing the transistors whose parameters have slight influence on the output voltage. This is why the fault diagnosis process should be preceded by the sensitivity analyses.
The proposed method has been compared with the methods recently published in references [18] and [20] devoted to similar problem. They will be named M2016, M2014 and M2015, respectively.
At first we concentrate on the methods M2016 and M2014. To perform the comparison, method M2014 has been implemented to allow diagnosing CMOS circuits designed in nanometer technology, comprising the transistors characterized by the model BSIM 4.6. All 30 fault diagnoses included in Tables 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 providing the results found by method M2016, have been performed using method M2014 with the same diagnostic tests and the assumed measurement accuracy and the parameters /, n, k max as in [18] (Example 1). On the basis of these experiments the following conclusion can be drawn. Method M2014 is very sensitive to the tests and in numerous cases several tries must be taken to select the proper one. Moreover, sometimes this method requires more than one measurement node. In the great majority of cases method M2014 is more time consuming than method M2016. To be specific, let us consider in detail Example 1. For the diagnoses included in Tables 1, 2, 3 the results given by method M2014 are very similar to the ones provided by method M2016 (see Tables 12,13,14). In all cases, except one, method M2014 consumes more CPU time which is 1.48-6.64 times longer. For the cases presented in Tables 4, 5 method M2014 fails. However, it is possible to arrange another tests so that the method works and gives correct results. Unfortunately, the tests relating to the diagnoses indicated in Table 5 requires access to two measurement nodes.
Method M2015 comprises very large class of circuits, including bipolar and CMOS ones, designed in micrometer and submicrometer technologies. In Ref. [20] the MOS transistors designed in nanometer technology are characterized by PSP103.1 model introduced into DELPHI environment. Thanks to this the circuit analyses are executed using a dedicated program written in DELPHI, that considerably improves the computation process and makes the method sound. To compare with M2016 the method M2015 was implemented including BSIM 4.6 modeled MOS transistors and circuit analyses were performed in IsSPICE 4. Method M2015 requires numerous sensitivity analyses that in this case must be performed using the brute-force incremental approach. In consequence this method needs large computing power and consumes much CPU time. Thus, method M2016 is less universal than M2015 but, in the case of CMOS circuits with BSIM 4.6 modeled transistors, faster and easier to implement. To be specific, all the cases presented in Tables 1, 2, 3, 4 were retaken using method M2015 with h ¼ 0:05. The method gives the results very close to the ones provided by M2016, but the CPU time is 7-45 times longer.
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