The discovery of a third breakdown: phenomenon, characterization and applications

In the history of metal–oxide–semiconductor field effect transistor (MOSFET), the quality of its gate oxide has been a cornerstone of the present semiconductor integrated circuits. The changes of gate dielectrics from conventional SiO2 gate oxide into high-k materials has brought us more challenges in various aspects of transistors, especially the reliability improvement when MOSFET dimension is continually scaled. Depending on the making of high-quality gate dielectrics, it plays a major role for the manufacture of high-end CPU with ultra-low power and low leakage, nowadays. There are two major well-known breakdowns in MOSFET’s history. Not until 2015, a world first observation of the breakdown, different from soft and hard breakdown, named dielectric fuse breakdown, dFuse, was discovered, as a result of CMOS technology moving into the high-k metal-gate (HKMG) era. In this paper, we will introduce from the inception of the Ig-RTN (random telegraph noise) measurement on the understanding of breakdown in 2008 and briefly describe the fundamentals of the RTN technique. Later in 2015, a version 2.0 of this Ig-RTN measurement, named Ig-transient, was successfully developed to delineate the breakdown path in HKMG transistors, from which a third breakdown, named dielectric fuse breakdown, was discovered. Its origin and physical mechanism have been discussed. This breakdown relies on the understanding of a leakage path in the gate dielectric of MOSFET, especially the movement of oxygen ions and the oxygen vacancies in the gate dielectric. Sophisticated measurement technique has also been developed to identify the traps generated in the gate dielectrics which laid the foundations on the understanding of trap generation as a function of time. In the end, two major applications in memories are presented, one is in the use of one-time-programming memory and the other on the understanding of the switching phenomena involved in the operation of resistance random-access memory (RRAM).


Introduction
In the history of transistor's scaling, at the beginning of 2000, the development of high-k dielectrics marks a new era of the complementary metal-oxide-semiconductor (CMOS) technology by the changing of gate dielectric from traditional SiO 2 into high-k dielectrics [1][2][3]. Its main purpose is to solve the leakage current through the transistor's gate. This brought us to a further development of the technology towards a new era of the so-called high-k metal-gate (HKMG) CMOS generation. This is a cornerstone of the development for high-performance CPU [4] such that portable devices, e.g. mobile phones, notebook and PADs, become possible in the wireless world. In addition to the usage of high-k material to reduce the gate leakage in an ultra-low power design of integrated circuit chips, much more attention has been raised on the study of gate dielectric reliability in metal-oxide-semiconductor field-effect transistor (MOSFET).
In terms of MOSFET's reliability, time dependence dielectric breakdown (TDDB) [5,6], bias temperature instability (BTI), mobility degradation [7] and stress-induced leakage current (SILC) [8] are major concerns, in which stress-induced leakage current (SILC) has been a critical issue in the power consumption of CMOS devices. A huge number of published articles have stressed the importance 1 3 124 Page 2 of 15 of how to suppress the level of gate current in high-k dielectrics. Numerous high-k materials have been investigated to further reduce the gate leakage current [9][10][11]. Some studies focused on how to improve the interfacial layer between high-k materials and the Si substrate to reduce the gate current [12,13], while some others studied the way to control the gate leakage current by modification of the physical characteristics of high-k materials with co-implantation of ion species [14]. These results led to the manufacturing of the HfO 2 -based dielectrics as the mainstream of gate dielectrics in replacing traditional SiO 2 gate dielectric in advanced CMOS devices at 45 nm generation of CMOS technologies [3].
In this review paper, first, we will introduce the basics of Ig-RTN [15,16], which provides foundations to examine the traps existing in the gate dielectric of the transistor. These traps provide us an understanding of the physics or mechanism behind the aforementioned gate leakage as well as stress-induced BTI, TDDB, SILC, etc. Especially under the TDDB test, two critical breakdowns, i.e. soft breakdown and hard breakdown [17], are the major breakdowns of the transistor that were focused on in the 1990s. The inception of the Ig-RTN measurement technique that was developed by our group served as an important tool to understand the breakdown mechanism of the gate dielectric [15,16]. Later, a new version of Ig-RTN, named Ig-RTN measurement technique Version 2.0, was elaborated [18], which has been able to observe the trap generation as an evolution of time. This led us to the discovery of a third breakdown, different from soft breakdown and hard breakdown, named as dielectric fuse breakdown (dFuse) [19]. This paper will be organized as follows. In the next section, the fundamental of Ig-RTN measurement technique [15,16] will be introduced first, from the observation of experimental data of high-k gate dielectric transistors. In Sect. 3, also, from the experimental observations, we will explain the theory on how to measure the trap generation as a function of time, which led to the development of Ig-RTN transient measurement, Version 2.0 [18]. A methodology has been elaborated to depict the breakdown path of gate dielectrics in MOSFET. Here, the concept of leakage which led to the soft breakdown and hard breakdown, and the third breakdown will be described and differentiated [20]. Finally, in Sect. 4, the application of this newly developed third breakdown (dFuse) to the development of OTP [21,22] memory and the understanding of the operation of resistance memory will be discussed. In the end, a summary and conclusion will be given in the last section.

Fundamentals of Ig-RTN
Random telegraph noise (RTN) is a switching phenomenon of electrical characteristics in a transistor caused by the capture and emission of carriers by the oxide trap, as shown in Fig. 1, which can be measured by I d -or I g -RTN (Fig. 1b), [23,24]. RTN signal, in the form of repetitive digital waveform with two or more levels, depends on the number of traps [24]. In the following, we will examine first the properties of RTN traps in a high-k gate dielectric. The location of the traps in the MOSFET is strongly related to the conduction path in the gate dielectric, i.e. filament. Also, the conduction path is caused by the breakdown. Figure 2a is the experimental observation of the transient behaviour (i.e. gate current) in the gate dielectric with the evolution of time in a high-k MOSFET [20]. The gate dielectric has EOT (equivalent oxide thickness) = 1.35 nm, composed of an HfO 2 with thickness 2.8 nm and an SiO 2 interfacial layer with thickness 1.2 nm, under long-term stress of positive-bias temperature instability (PBTI) [14]. It was observed that there were  Fig. 2b. These switching behaviours came from the interaction between electrons in the Si substrate and trap in the gate dielectrics [18]. The switching mechanisms can be considered as electrically short or open for the gate after long-term stress [25,26]. When the internal path is electrically short, the diffusion of oxygen ions from the dielectric bulk to the metal gate creates more oxygen vacancies and increases the level of gate current. This represents the process from soft to hard breakdown. On the contrary, the gate current is reduced when the oxygen ions move back from the metal into the gate dielectric, i.e. electrically open, implying a different breakdown, called dFuse breakdown which will be explained later. As revealed in Fig. 2b, the breakdown path is assumed to be a percolation path of the traps which are connected together to form a filament, that is, a conduction path with traps nearby. The traps serve as a switch to control the current flow through the filaments, in which the trap location is responsible for the magnitude of the current flow.

Quantization of the measured RTN signal
First, a two-level RTN of the gate current (Ig) can be measured from which the trap in the transistor gate dielectrics can be well analyzed [15]. When there is only a single trap, as shown in Fig. 1a, a two-level gate current in the dielectric can be measured such that the trap location can be identified. The two characteristic times of the I G current are defined as: (1) capture time, τ c , for high current level, and (2) emission time, τ e , for low current level, as shown in Fig. 1b, where the current, I G , versus time, with a two-level waveform is illustrated.
In Fig. 1c, when the trap is empty, a larger current going through the dielectric can be measured; in contrast, the gate current becomes smaller with electrons captured in the trap site. The reason is that when the trap is filled (occupied) by electrons, a smaller current is expected, since the trapped electrons serve as a blockade of the tunnelling current. The amplitude, capture, and emission time are the key parameters of the random telegraph noise (RTN) signal depending on the trap properties, such as the trap depth into dielectrics and the trap energy level apart from the conduction band. We can extract the trap position by analysing the capture and emission time from the measurement [15]. A typical example of a single trap RTN signal is shown in Fig. 3a, where the I G current fluctuation is caused by a trap located in the gate dielectric.

Location of the trap
To determine the location of a single trap, the details of the calculation can be found from Refs. [15,23]. The summarized result in the vertical direction of the trap location is given. From the measured RTN signals, as in Fig. 3a, the trap location above the silicon interface, Fig. 3b, Z T , can be calculated from the slope of the plot, for varying gate biases, i.e. From Eq. (1), Z T can be calculated. Figure 3b shows the τ c vs τ e plot from the measurement where the slope of dln(τ c /τ e )/dV g gives the depth of the trap. In the high-k gate dielectrics, more complicated formulae need to be re-derived for a composition of a high-k material with an SiO 2 interfacial layer; please refer to [20] (e.g. Table 1).

The concept of leakage path from experiment
After applying BTI stress on MOSFET at various bias or temperature conditions, we will be able to generate traps in the gate dielectric. Figure 4 shows the generation of traps under short time BTI stresses of n-channel MOSFET (e.g. V gs = 2 V, 85 °C, for 50 s). Once we take a measurement of a two-level Ig current and its variation as a function of time at different Vgs biases, we may calculate the normalized amplitude of variation of the gate current (∆I g /I g ) for various traps, as shown in Fig. 4a for the MOSFET in the inversion region of operation. But, in the deeper region close to the Si channel region (i.e. inside SiO 2 ), MOSFET i.e. when the trap is empty, the I g current is at high level, while when the trap is filled, the I g current remains at low level accumulation region traps can be measured as given in Fig. 4b. Figure 4c shows the location of the traps in the energy band diagram. Then, we may assume that a leakage path or filament is formed surrounding the generated traps. Moreover, according to different distances from the coverage of the trap potential to the gate current path, the fluctuation of gate current will be affected by the trap location. If the trap is very close to the path, the fluctuation will be very large, or it will be smaller when the trap is far away from the path. In this case, it is believed that the trap a is closer to the path than trap c. More importantly, the gate current path can thereby be traced by the traps. As a result, as the stress time progresses, the gate leakage current path will grow near the traps in dielectrics, and the gate current increases with larger amplitudes of fluctuations. In short, as long as we can identify the trap location from the gate through the dielectric and to the silicon substrate, we can always draw a leakage path or a synonym of filament responsible for the leakage current. Figure 5a shows the measurement setup, named Version 2.0 Ig-RTN, i.e. Ig-RTN transient measurement technique [19], which is used to profile the generation of traps as a function of time. First, constant voltage or current stress was  Table 1 The comparison between dFuse breakdown and anti-fuse breakdown. For dFuse, the gate dielectrics become porous at the IL (interfacial layer), different from the other two breakdowns  teristics of two different types of leakage current. Black curve shows many levels of gate current for softer breakdown to happen, leading to longer time to breakdown. The red curve exhibits fewer levels of gate current with shorter time to breakdown provided and then held for performing I g -RTN measurement [18] to detect the traps when ramped voltages were applied gradually. It was repeated until the dielectric went to breakdown state. After gathering traps at a specific time, one can determine the physical location of the generated traps in the dielectric. These trap locations may be identified as time progresses until the dielectric reaches breakdown.

BTI-induced breakdown path in nMOSFET (low stress)
First, we apply a constant voltage stress on the MOSFET, a little higher voltage than the normal operating voltage V DD (e.g. for a 28 nm CMOS technology, V DD = 1.8 V), under V gs = 2.4 V at room temperature, see Fig. 5b. At 10 s, we may detect a trap #1, close to the SiO 2 interface. In the next 10 s, it generates a second trap, #1.2. After another 30 s, several traps, #2.1 and #2.2 are generated. We repeat the same procedure until the gate dielectric reaches breakdown. The total accumulated time is 660 s. The formation of a filament was drawn from #1 to #8 and finally reached the top gate of MOSFET. We can see more randomly generated traps around the interface between the interfacial layer and the high-k layer, and the final trap is generated near the gate terminal. It is attributed to the defective interface and the weak region of the interfacial layer that generate these traps. The first few traps were generated near the interface of HfO 2 and SiO 2 and then the circle around at this interface. Eventually, as time progresses further, it reaches breakdown. The dashed area is in the shape of a spindle [18].

BTI-induced breakdown path in nMOSFET (high stress)
Next, a different stress test, called BTI stress at V GS = 2.45 V and 125 °C, on the same MOSFET was performed. Figure 5c demonstrates the experimental result of a constant voltage BTI-induced breakdown path. It shows a different path from the previous one (Fig. 5b), in which the trap was generated at the interface of SiO 2 and the Si substrate, and then most of the generated trap is a single trap. In a shorter time, it reaches breakdown. The latter is hard breakdown (Fig. 5c) and the former (Fig. 5b) is soft breakdown. Figure 5b, c shows different forms of the gate leakage path. The former generated traps with longer time and forms a spindle-shaped filament (path). The latter exhibits a snake-walking behaviour, named "snake path".
To differentiate between the two results in Fig. 5b, c, we made a plot of their gate current transient for a comparison, as shown in Fig. 5d. The black-coloured curve represents the case of spindle shape and the black-coloured curve shows the case of sneak shape. It can be clearly observed that, for the black curve in Fig. 5d, there are many levels of gatecurrent fluctuation, contributed by the corresponding traps induced by I g -RTN in the dielectrics before the breakdown. In comparison, the red curve shows few levels of gate-current variation, which fits into the result of Fig. 5c, and its time to breakdown is shorter accordingly. In other words, the black-coloured curve maintains a longer time for the soft breakdown before reaching eventual hard breakdown.
As a consequence, two types of breakdown paths can be identified from their leakage paths as seen from the schematic in Fig. 6a. Type 1 forms a path with spindle shape, which induced the defective interfaces in the early stage under moderate stress. Type 2 forms a snake-walking path under high strength of stress, as a result of hard breakdown (HBD) [18]. Both types of breakdown paths show different slopes in the time-to-breakdown plot (Fig. 6b). Obviously, soft breakdown requires more time to reach hard breakdown as we commonly believe. Figure 7 shows the summary of the above experiments in their lifetime prediction. Two significant parameters affect the formations of gate-current paths: temperature and the intensity of the stress field. Between the two boundaries, the intensity of electric field dominates. Also, there is a turning point defining this two-slope curve. If the intensity of field is lower than the turning point, the

The discovery of a third breakdown: dielectric fuse breakdown
Based on the mechanism of the above soft breakdown and hard breakdown that people usually understood, the transistor will go into soft breakdown first and then develop into a hard breakdown for the gate dielectric to fail. This hard breakdown will cause a permanent failure of the gate dielectric. The leakage path becomes short as a result of a huge current measured between the MOSFET gate and the drain/source. However, by taking advantage of the generation of traps at the interfacial layer (e.g. Fig. 5b), we developed further an experiment in Fig. 8a from which a different breakdown was observed. In practice, in the measurement of Fig. 8a, we applied a higher voltage and shorter duration of pulse on the MOSFET gate, i.e. a higher electric field across the high-k/interfacial gate dielectric. The gate dielectric became open and the gate current will be pulled down to a very low level (clockwise); on the other hand, it will be raised to a higher level, labelled as anti-fuse (counter clockwise), i.e. short. The latter, anti-fuse, is evidence of hard breakdown, consistent with Fig. 5d, leading to an increase of the gate current after breakdown. On the contrary, with an increase in the applied voltages, the gate current dropped to a very low level, because the gate dielectric reached breakdown in a certain way, i.e. during the process of trap generation, oxygen ions were annealed out and more oxygen vacancies were left at the interfacial layer. This led to a break of the filament between the gate and drain, located inside the interfacial layer, since SiO 2 has lower permittivity and thickness and is weaker than the high-k HfO 2 layer. As a consequence, after the burn-out of this interfacial layer, the SiO 2 layer exhibits porous structure. Also, there is an evidence that it can be proved by the OBIRCH (optical beam-induced resistance change) spectroscopy. As seen in Fig. 8b, it was found that the anti-fused one (left) shows hot spots, indicating a short circuit of the gate dielectric in the image. However, on the right-hand side dielectric fused case, we did not see the spots, implying that no current went through the gate. Both observations show that gate dielectric interfacial layer is broken (i.e. equivalent to an open gate) in contrast to a short gate of anti-fuse. Therefore, we gave it a name, a so-called third breakdown-dielectric fuse breakdown, dFuse [19]. The location of hot spots identified by optical beam-induced-resistance change (OBIRCH) technique in the case of anti-fused, but no hot-spot was found after dielectric fuse In practice, to further understand the path development during the dielectric fuse breakdown, I g -RTN transient can be utilized to measure the generation of traps as a function of time [19]. Thus, we can monitor the generation of traps under certain stress conditions. Figure 9a shows the results after the dielectric fuse breakdown. Traps are generated at the interface of the high-k/interfacial layer (IL), but if we increase the temperature to 85 0 C, i.e. with a higher stress, Fig. 9b, the traps are generated towards the SiO 2 /Si interface and the SiO 2 layer is considered to be open under such circumstances. As a result, these IL traps create a porosity in SiO 2 and eventually a gap to block the current path, resulting in a sudden decrease of the gate current, as shown in Fig. 8a (blue-coloured curves). A summary of three different breakdowns that we discussed so far can be compared in Table 1. The dielectric fuse, dFuse, that we observed can be achieved by a higher voltage, but shorter pulse across the gate and drain of the storage transistor, which is different from the traditional hard breakdown or soft breakdown (columns 2, 3).

One-time programming memory
By taking advantage of the dielectric fuse breakdown, the first application was the development of one-time programming (OTP) memory, i.e. a memory with the feature for write once, but can be read multiple times. The architecture of an OTP as a unit cell, as shown in Fig. 10a, consists of a control transistor (T1) and a second transistor (T2) serving as storage. By applying a pulse with 4.2 V high voltage and 1 μsec duration to the gate (T2), it is sufficient to create a dielectric fuse breakdown (dFuse) of the gate dielectric of transistor T2. This is the programming operation, i.e. write. Then, we will be able to read the drain current of T2 with suitable bias on T1. This is regarded as read operation.
Note that when the gate dielectric is rendered into dFuse breakdown, the gate of the T2 transistor has no control over the channel, and a low drain current (I d2 ) is observed. On the contrary, when the gate dielectric of T2 is not broken, a high drain current (I d2 ) can be measured. These two currents have the I d2 -V WL characteristics as shown in Fig. 10b, which represent a logic 0 and 1, respectively. Since the gate dielectric is ruptured with a condition of dFuse, it creates a permanent failure of T2 from which T2 remains at logic 0 and cannot be recovered. So, this kind of memory is named as one-time programming. An example of the MACRO design [27] is shown in Fig. 10c, in which a unit cell consists of a control transistor in the middle and the other two neighbouring transistors as the storages on either side, i.e. one bit is only 1.

T (transistors).
This OTP provides us several applications, Fig. 11, in the IoT era, such as key encryption, device identity, code storage in mobile phone, power management in mobile phone, LCD drivers, code storage in MCU (microcontroller unit), etc.    Two different levels of the measured currents, I d2 , represent two logic states. c A macro design of OTP memory array Fig. 11 The one-time-programmable (OTP) memory has various applications in the IoT era soft-breakdown phenomenon and recoverable, such that it can be used as a nonvolatile memory. This RRAM can be switched between low-resistance state (LRS) and highresistance state (HSR), which is the basis of a memory to be operated between logic 0 (LRS) and 1 (HRS). The filament formation varies during the memory operation, i.e. the filaments are different for different LSR and HRS states. Also, soft breakdown is the dominant mechanism in the switching process. Although in the past several studies, fast Fourier transform of TEM picture, [28] low energy EELS plot [29], have been reported to understand the filament formation, the filaments path has not yet been clear.
To understand the switching of the RRAM, knowledge of the measurement techniques of MOSFET as previously mentioned will be sufficient to clearly demonstrate the switching of RRAM and understanding its filament formation.

Experimental observations
A typical RRAM device, in the form of a bilayer MIM structure, was prepared by the deposition of a 6 nm HfON on 1 nm Al 2 O 3 between TiN as the top electrode (TE) and Pt as the bottom electrode (BE) before 400°C and 3 min post-metal annealing (Fig. 12a, b). The area of the device is 0.1um 2 . Figure 12c shows its typical I-V characteristics, named as a bipolar operation [30]. As shown here, there are two processes in RRAM: SET and RESET. The process which makes the device reach a low-resistance state (LRS) is called SET. In contrast, the process which makes the device reach a high-resistance state (HRS) is called REET. During SET and RESET processes, we need to apply positive or negative voltage, respectively, depending on the switching type of RRAM. An example of bipolar operation is shown. Figure 13a shows an experimental observation of an RRAM under different constant voltage stresses, in which soft breakdown is the dominant mechanism. As previously mentioned, the soft-breakdown process contains many RTN traps in the dielectric. So, I g -RTN transient technique has been elaborated to locate traps during the breakdown process. It is believed that RTN traps are located in proximity to the breakdown path. From the zoom-in figures, Fig. 13b-d, we suggest that RTN traps are deeply involved in the transition mechanisms of LRS/HRS states. Therefore, thanks to the possibility to locate the trap by the I g -RTN transient technique [18], in the following we will demonstrate how to trace the filament path during the switching of resistances [31].

The observation of filament growth of an RRAM during forming
Using the forming of RRAM as an example, we applied a constant high voltage stress on the top electrode of RRAM, with the bottom electrode grounded for a short duration (e.g. 1us), following the procedure shown in Fig. 5a. The forming process is made by a positive sweep on the top electrode, as shown in the blue curve. After the forming, the RRAM resistance was changed to a low-resistance state (LRS). To RESET the resistance from LRS to a high-resistance state (HRS), a negative sweep voltage on the top electrode was applied, as shown in the red curve. Then, the resistance state can be SET to LRS again by a smaller positive sweep, as shown in the black curve. The operating voltage of RESET and SET is − 3 V and 2.5 V, respectively, and the maximum operating current of SET and RESET is 0.1 mA and 0.4 mA, respectively. Figure 14a shows a two-level RTN signal in which the generation of trap #1 to #2 is represented. At the next time period, Fig. 14b, four-level RTN signals were generated. It was found that trap #3 and trap #4 were involved in the transition simultaneously. These are strong evidences that many more traps are involved as time progresses. Figure 14c shows the plot of ln(τ c /τ e ) versus voltages of TE as the horizontal axis. If ln(τ c /τ e ) > 0, it represents that traps are interacting with TE. If ln(τ c /τ e ) < 0, it represents that traps are interacting with BE in Fig. 15 [31]. Figure 3.15a shows the profile of the filament during the forming of an RRAM device. It was observed that there were two trap-accumulation paths induced by electrons and vacancies, respectively. The electron-induced path interacts with the top electrode, while the oxygen vacancy-induced path interacts with the bottom electrode. The grey region is the filament which is confined to these two paths. In Fig. 3.15b, it shows the measured current transient with evolution of time. It reveals how the filaments are formed in four stages. In stage 1, there are fewer traps in dielectric and they are spread out randomly. In stage 2, a huge increase of the leakage current proves that the traps are generated near TE and BE. In stage 3, the leakage current remains almost the same, but it was observed that many RTN signals were generated. It can be considered that the filament is almost connected between TE and BE. Finally, in stage 4, a complete filament is formed, which caused the current jump up to a very high value and be limited by the compliance current.

The filament growth of an RRAM during RESET/SET
As we described above, we may also take similar steps to examine the filament formation during RESET and SET operations furthermore. After the forming of an RRAM, it is at low-resistance state (LRS). Then the RESET operation would be performed to reversely switch the resistance to the high-resistance state (HRS). A negative constant stress voltage of V top = − 3 V under the environment of 25 °C was applied to the TOP electrode, to complete the RESET operation. In Fig. 16, we can still observe a two-branch filament during the RESET process. The distribution of RTN traps which comprise the RESET filament is almost the same as the forming filament in Fig. 3.15a, except in the region near the top electrode. In this region, RTN traps disappeared, since mobile oxygen ions move away to the TiN of TE with oxygen vacancy left in this region, i.e. no RTN traps exist in the region near the top electrode, indicating that the filaments were cut off in this region. In other words, there are two critical regions, one near the TE, called "the neck", and the other one close to BE, called "the waist". It is reasonable to assume that the current in the filament will be cut off once the neck disappears and the neck length is approximately 1.5 nm. This broken neck creates the HRS of the RRAM.
On the other hand, for the SET operation, it was found that the filament growth was different from those originally created filament paths during the RESET operation. Figure 17a shows a filament path during SET operation. We can observe that the SET path is narrower than original forming-created broader filament. The reasons are the transient low-resistance state characteristics during the cycling operation, as shown in Fig. 3.17b. At the beginning, the values of resistance are kept at a relative low level, but gradually increase and converge to a more stable high level state  during cycles. In other words, the filament path during the SET operation seems to train itself from the initial wider and unstable forming-created path to a narrower and stable path. Since the forming-created path is wider, the corresponding resistance state at the beginning of the transient result is lower, with reference to the higher and more stable resistance state induced by the final narrow self-trained filament of SET.

The dielectric fuse path
As previously mentioned, when we apply a higher negative voltage stress on the RRAM device, it will induce a dielectric fuse. It is based on the concept that a lot of traps are created in the dielectric and it becomes porous, since the RRAM structure in Fig. 3.18a is similar to the gate dielectric of a MOSFET with a bilayer HfO 2 and interfacial layer SiO 2 . By employing the Ig-RTN transient technique, we may trace the filament path during the dFuse operation. The evidences are revealed in Fig. 3.18b. Many traps were generated and gathered around the thin Al 2 O 3 dielectric and the interface between HfON and Al 2 O 3 . After a numbers of cycles, the dielectric around this region will burn out, yielding to the breakdown of the dielectric with lower permittivity (e.g. Al 2 O 3 in this case). This is the reason why a very low current was measured after the dielectric fuse breakdown, as shown in Fig. 3.18a. The cartoon in Fig. 18b shows a porous structure in the Al 2 O 3 dielectric, marked as dFuse. This implies that we can use this dFused state (blue symbols) as a logic 0, while the set state with LRS is regarded as logic 1, for OTP development.
In summary, in this section, we have demonstrated a bilayer RRAM device, which can be tuned into three states, SET, RESET and dFuse. The operation can be understood from the unique structure of dielectrics. HfON is in charge of normal SET/RESET operation and Al 2 O 3 is in charge of dFuse operation. Results demonstrated that the filament of RRAM can be experimentally profiled as a cone-shaped path with the neck near TE and the waist close to BE. Three kinds of operations, forming/SET/RESET, can be understood Fig. 17 a The path of SET is narrower than the original filament path (pink colour), i.e. forming-created path is broader, while SET exhibits a narrow filament region. b The transient LSR characteristics dur-ing the cycling operation. During forming, the filament is wider and during SET operation it tends to self-train from the initial wider and unstable forming-created path to a narrower and stable path Fig. 18 a The DC sweep characteristics in SET/RESET/dFuse state. b During dFuse, traps are generated at the interface of Al 2 O 3 /HfO 2 , which eventually lead to a porosity of Al 2 O 3 with lower permittivity and dFuse was observed through the characterization of traps and filament formation. During SET, the filament near BE becomes narrower and convergent to a stable state; in RESET, the neck of the filament is broken, where the accumulated traps are filled with oxygen ions diffusing back from TE. This concept can be used to explore more fundamental understanding of the reliability of RRAM. Moreover, when dFuse is incurred at the interface between HfON and Al 2 O 3 , more traps were induced, leading to a cutoff of the current. After realizing the physical mechanisms of RRAM, we may also design a new type of OTP by taking advantage of the dFuse observed in RRAM with a larger memory window (i.e. a large window between Logic 0, LRS, and Logic 0, dFuse).

Summary and conclusion
In summary, in the year around 2007, traditional SiO 2 gate oxide was replaced by the high-k metal-gate technology of CMOS at the 45 nm generation in production [4]; more reliabilities need to be taken care of at that time. This HKMG technology paves the way for the current high-performance CPU, GPU, and MCU used in the portable devices. The 45 nm HKMG generation is a milestone in human civilization moving to a better world in terms of energy saving, high performance automotive, high security, AI, IoT, and autonomous industry. The HKMG generation also provides more opportunities to understand the physics and reliabilities which are different from the past generations with SiO 2 as the gate dielectric in MOSFET for over several decades.
Moreover, since the first version I g -RTN measurement technique was developed in Refs. [18,19], it brought us more opportunities to understand the reliability of breakdowns, from soft breakdown, hard breakdown, to dielectric fuse breakdown. In the course of the study, it took almost 6 years for us to develop the Ig-RTN transient technique, a version 2.0 of the very first version in 2008. This led to the discovery of a third breakdown, named dielectric fuse breakdown. Then, we will be able to distinguish the differences among the three different types of breakdowns. In particular, both the first version and version 2.0 Ig-RTN allow us to understand the reliability physics underlying the everincreasing leakage in HKMG CMOS as scaling of transistor continues. Since the high-k gate dielectrics of MOSFET is similar to MIM in RRAM, the developed techniques can be well developed to understand all the three breakdowns. Moreover, the dFuse that was discovered by us in this series will soon find its major applications in hardware security, such as the OTP [27], physically unclonable function (PUF) [32], and for use in mobile phones and MCU, such as in power management, cryptography, key generation, and encryption.
Acknowledgements The author would like to thank the team members C. M. Chang, M. H. Lin, P. Y. Lu, Z. H. Huang, S. P. Yang, E. R. Hsieh, H. W. Chen, C. W. Chang, C. C. Chuang, H. W. Cheng, who, during their course of study in pursuit of their degrees in either master's or Ph.D. program, made contributions to a series of research works in MOSFET reliability and resistance memory. To let the reader to have a whole picture of the discovery and potential commercialization of the OTP memory using the third breakdown, this paper provides a quick review of our previous work. Also, we would like to acknowledge the support from the Ministry of Science and Technology, under contract No. MOST-111-2218-E-A49-018-MBK.

Data availability
The data presented in this study are available from the corresponding author upon request when it is appropriate.
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