An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator con-tributes signiﬁcantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2–3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18- μ m CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.


Introduction
Analog comparator is an intermediate element between the analog and digital domain of an analog-to-digital converter (ADC). The main comparator parameters such as resolution, speed, and noise directly affect the quality of analog-to-digital (A/D) conversion. Two other parameters, namely power consumption and area, become particularly important for circuits with high number of ADCs. The representative examples of such systems are CMOS image sensors (CISs) [10,16,19,20,22], especially massively parallel CISs [5,[11][12][13]15,21]. For the latter, A/D conversion is implemented at the pixel level, as illustrated in Fig. 1a. Here, the power consumption and the area of a single pixel should be sufficiently small to minimize the total chip size and power consumption which are both proportional to the number of pixels and become nonnegligible even for a low-resolution sensors containing up to tens of thousands of pixels. For those reasons, a single-slope ADC is preferred for in-pixel implementation because it is simple and can be fitted within several hundred square micrometers of silicon surface. A complete N-bit single-slope ADC consists of an analog comparator and an N-bit time-to-digital converter (TDC) as illustrated in Fig. 1b. The TDC can be implemented as a fully digital circuit (e.g., as an N-bit counter), and, therefore, minimizing its layout area and power consumption is relatively easy, as opposed to a comparator, which is an analog circuit with very limited potential for area reduction.
Let us investigate the power consumption for two different types of CMOS comparators shown in Fig. 2: continuous time and discrete time (dynamic). The classic continuous-time comparator (Fig. 2a) consists of a MOS differential pair, biased by a current source, and of an additional gain stage [1]. In the ADC from Fig. 1b, such comparator draws a mean current of I bias during the entire interval time T ramp . One can say that until V ramp becomes equal to V sense , as well as after that time event, the Examples of the classic CMOS comparators: a continuous-time comparator with a differential pair [1], b discrete-time (dynamic) comparator with a latch [1,3,4] comparator dissipates electric power in vain. The power dissipation can be reduced, e.g., by reducing the bias current. However, the current can be decreased only to a value that still provides the required slew rate (SR) at the comparator output and is related to the desired A/D conversion rate. In addition, an appropriate SR is necessary to properly control the digital circuits without excessive short-circuit currents in their operation. Because of these limitations, the power consumption of a continuous-time comparator can dominate a total power consumption of an ADC (up to 90% of a total consumption [13]).
The conventional discrete-time (dynamic) comparator from Fig. 2b is a regenerative latch, which is periodically regenerated and latched by a clock signal [1,3,4]. This comparator draws current from the power source only when the state changes, similarly to a digital circuit. The energy required to change the state can be as small as in a digital gate. However, the application range of this comparator in a slope ADC from Fig. 1b is sub-optimal in terms of energy consumption per single A/D conversion. The main reason for this is that throughout the time interval, T ramp , a discrete-time comparator needs to check a voltage difference, V sense − V ramp , at regular intervals determined by the clock. It can be easily shown that the number of comparisons performed by the comparator during a single A/D conversion cycle is on the order of 2 N . For example, for a 10-bit converter the comparator performs 1024 comparisons. Each comparison (regeneration + latch) is related to the consumption of energy. As a result, the total energy consumption of this comparator may be comparable to that of a continuoustime comparator. Furthermore, multiple state transitions cause kickback noise which may become too high for a photosensor signal.
The energy consumption of both comparators can be reduced by power-down mechanism, which disables them after V ramp and V sense become equal. With this method, however, the energy required per A/D conversion of an image can only be reduced by half. This can be explained as follows. The comparators assigned to the pixels with low illumination power (higher V sense ) are active during a short time and consume little energy. Whereas the comparators with pixels with higher illumination power (lower V sense ) are active for a longer time and, therefore, consume more energy. In a long sequence of image frames, the count of light and dark pixels is similar, and, therefore, the power consumption of the entire array of pixels is reduced only by 50%.
This paper proposes a new solution for a dynamic CMOS analog comparator, which changes its state only once during a single A/D conversion in a slope ADC. As a result, power consumption of the comparator is about 2-3 orders smaller than in the conventional continuous and dynamic comparators. Furthermore, the proposed comparator meets the remaining requirements imposed on the in-pixel implementation, namely simplicity, small surface area, and no need for power-down mechanism. The paper presents different versions of the comparator, differing in terms of resolution and power consumption. For all circuit implementations in 0.18-μm CMOS technology from AMS, detailed simulations have been carried out under a power supply voltage of 1.8 and 1V, respectively. A detailed comparison of the proposed comparator with two other conventional comparators is also given.

Proposed Ultra-Low-Energy Analog Comparator
In the following Sects. 2.1-2.8, the operation principle of the proposed comparator is explained and its main electrical parameters are analyzed in detail.

Principle of Operation
Schematics of the proposed dynamic comparator in two-, three-, and four-stage versions are shown in Fig. 3a-c. The consecutive versions differ in resolution and energy consumption per state transition. The first stage of the comparator consists of an nchannel transistor (M comp ) and a p-channel transistor (M 2 ). The transistor M comp is the main device which compares V sense with V ramp . The M 2 is to precharge the parasitic capacitance C 1 to the voltage V DD . The consecutive gain stages are composed of dynamic inverters with parasitic capacitances C 1 , C 2 , and C 3 at their outputs. The capacitance loading the comparator output is denoted as C load .
The comparator operating principle is as follows. Let us assume that the voltage V sense is in between 0 V and V DD . The initial value of V ramp is V DD , and, therefore, M comp is switched off. The capacitances C 1 and C 3 are initially precharged to V DD by the pulse of RST, and the capacitances C 2 and C load are discharged to 0 V by RST. The A/D conversion is initialized and V ramp starts falling from V DD to 0 V in a period T ramp . When the falling ramp descends below where V TH is the threshold voltage of M comp , M comp starts conducting the current which discharges C 1 . The voltage change on C 1 is amplified by the consecutive inverters. As a result, the comparator output voltage V out changes at high speed. Energy consumption of the comparator during its state transition is associated only with recharging the parasitic capacitances and can be given by: As explained above, the proposed comparator changes its state only once for the entire period T ramp . Consequently, the total energy consumed by the comparator in a single A/D conversion is equal to that given by (2).
It should also be noted that the ramp generator, even though it is connected to a source node of the transistor M comp , is always loaded by a high impedance (Z ramp ) approximately equal to a series connection of the channel resistance (r ds ) of M comp and the parasite capacitance C 1 , i.e., Z ramp ≈ r ds + 1/jω C 1 . The r ds varies widely within the ramp duration time (M comp is off and on), but Z ramp is always not lower than 1/jω C 1 . The ramp generator requires a buffer to drive only a capacitive load. The classical realization of such buffer, for example operational transconductance amplifier (OTA) with closed feedback loop, can be applied.
As explained before (Fig. 1b), the analog comparator in a slope ADC acts as a voltage-to-time converter, which translates V sense to a pulse duration time (T out ). With the origin of the time axis aligned with the start of the ramp signal, the comparator voltage-to-time conversion can be determined, taking (1) into account, as: where V ramp ranges from 0 to the supply voltage V DD , and V sense ranges from V TH to V DD . In modern CMOS technologies, the voltage V TH can be reduced even to 0 V, but "zero V TH " devices may have too large leakage for this application. In practice, this means that the lowest value of V sense is about 0.2-0.5 V, which is adequate for the use in image sensors, because the voltages below that value are not used in most types of the pixel photosensors [7,9,13].

Slew Rate and Resolution
The verification of a voltage resolution of dynamic comparators is more difficult compared to continuous-time comparators because the input-output DC characteristic cannot be plotted, and, thus, the voltage gain cannot be easily determined. If we restrict our considerations to the application of this comparator in a slope ADC, where it acts as a voltage-to-time converter, the required resolution of the comparator can be easily determined in the time domain. The comparator controls an N-bit TDC, and, therefore, it must make a decision (make a comparison) during the time interval T ramp /2 N . Assuming the comparator output is changing from 0 V to V DD , the required SR should be at least For example, for values of V DD = 1.8 V, T ramp = 1 ms, and 10-bit resolution, the required SR is 1.8 V/μs. This is not challenging because the comparator in the pixel ADC is loaded by a simple digital circuit (latch or gate) with low capacitance of up to tens of the femtofarads (fF). However, the SR depends not only on the load capacitance but also on the amplitude and the slope of an input signal. For a sufficiently large amplitude (e.g., 0-V DD ) and a slope (e.g., 100 V/μs) of V ramp , the comparators in Fig. 3 reach a SR of hundreds of volts per microsecond. However, in a real-pixel ADC [13], the comparator is stimulated by V ramp of large amplitude (0-V DD ) but with a relatively small slope (e.g., 1.8 V/ms). Under such conditions, the actual SR of the comparator may be multiple times lower as compared to its maximum possible because of insufficient voltage gain of this comparator. Moreover, some further reduction of SR and resolution of the comparators from Fig. 3 can be caused by the transistor leakage and subthreshold currents. This effect will be discussed in the following Sect. 2.3.

Optimization of Leakage, Slew Rate, and Resolution
The A/D processing time for a single pixel as long as 1 ms is sufficient for parallel architecture of the pixels array as in Fig. 1a operating at a rate of up to 1000 frames per second. Given the long processing time, the leakage currents (I off ) of transistors will result in an undesirable change in initial voltages at the comparator nodes. Since transistors in the subthreshold region show a voltage gain greater than one, even a small change in the initial node voltage, for example at C 1 , will be magnified and propagated through all consecutive stages to the output V out . As a result, the signal edges become smooth, as shown in Fig. 4, and SR as well as the comparator resolution becomes reduced which follows from (4). Increasing the nodal capacitances simultaneously minimizes the negative impact of I off and I subth . As a result, SR and comparator resolution improve. The propagation time of a comparator may become longer, but no more than a single nanosecond, and therefore, this effect can be omitted for further considerations.
To demonstrate the performance of the new comparator topology, a standard 0.18μm AMS CMOS technology was chosen and optimization of leakage currents, slew rate, and resolution was carried out. The following working conditions were assumed: processing time T ramp = 1 ms, C load = 50-500 fF, supply voltage V DD =1.0-1.8 V. In the optimization process, a key priority was to achieve the smallest surface area.
Dimensions of the transistors and the nodal capacitances resulting from the optimization are summarized in Table 1. For all transistors but M comp , a minimum channel width was selected. For M comp , a wider channel was used to limit the device mismatch. The channel lengths were chosen according to indications from above to minimize the impact of leakage. The parasitic nodal capacitances, resulting from p-n source/drain junctions and the gates of transistors, are increased by additional capacitors C 1 = 20 fF, C 2 = 20 fF and C 3 = 40 fF. These capacitors do not cause a significant increase in topology area because for their implementation small-size transistors are sufficient. For example, a capacitance of 20 fF can be implemented using the transistor of about 1.5 by 1.5 μm.

Simulation Results of Slew Rate and Resolution
The maximum SR value for all comparators from Fig. 3 is independent of the number of amplifying stages because it is determined by the current efficiency of the last stage.  The maximum value of SR obtained from simulations, while driven by a ramp with a short fall time T ramp = 10 ns, was 300 V/μs for two-and four-stage comparators, and over 800 V/μs for the three-stage comparator. The highest value of SR for three-stage comparator results from the fact that n-channel transistor is in the output stage.
When the ramp fall time is considerably longer, for example T ramp = 1 ms, the SR of the comparators decreases because it is limited by their voltage gain. Under these conditions, the best results are obtained for the four-stage comparator (12 V/μs) followed by the three-stage (2 V/μs) and the two-stage versions (0.3 V/μs). Taking into account the achieved SR values, the expected resolution of the comparators is 7, 10, and 12.5 bits for two-, three-, and four-stage implementations, respectively. These values, in turn, correspond to the input voltage resolution of 11 mV, 1.5 mV, and 0.3 mV for the full-scale operation range of 0-1.8 V. For a supply voltage reduced to 1 V, the resolution decreases to 6, 8.5, and 11 bits, respectively. The detailed plots of the simulated SR as a function of V sense for the selected supply voltages are shown in Fig. 5.
The proposed comparator can be used not only in a pixel ADC, but also for C load larger than typical 50 fF. Simulations indicate that the SR decreases for the larger C load . The corresponding SR plots are presented in Fig. 6. This effect is stronger for the four-stage comparator because its SR is not limited by the voltage gain but by its current efficiency. To drive the larger capacitance, the transistor in the output stage (M 7 ) should be widened. For example, to drive C load of up to 3 pF, the width of M 7 should be increased from 0.22 to 1 μm.

Simulation Results of Energy Consumption
The energy required to change the comparator state in all three versions with C load of 50 fF is below 0.5 pJ. This energy corresponds to a power dissipation of 0.5 nW for T ramp = 1 ms. The exact values of energy obtained from simulations are 180, 250, and 450 fJ for the two-, three-, and four-stage comparator, respectively. In Fig. 7, the detailed plots of the energy consumption as a function of C load for two selected supply voltages are presented. It is worth mentioning that the energy values obtained from the simulations and those calculated with (2) are practically the same.

The Influence of Body Effect at M comp on the ADC Linearity
Due to the body effect, the threshold voltage of M comp changes during the falling V ramp . The fluctuation of V TH differs for different V sense and results in the nonlinear voltage-to-time characteristic (3). This nonlinearity translates directly to the ADC nonlinearity. Fortunately, this effect is relatively weak. Figure 8a, b shows the voltageto-time characteristic and its derivative for the three-stage comparator. Its integral nonlinearity (INL) does not exceed 0.7% for an input voltage range of 0.2 V to V DD .
The human eye is not sensitive to nonlinearity of an image sensor in terms of gradient of gray, and, therefore, it is not an issue for most applications. For vision chips, for example, the most important is a high processing efficiency, while image quality is less critical [2,8,15,17,18].
If high linearity is required, then a comparator without the body effect should be used. In such a circuit, the main n-channel transistor, M comp , should be replaced by a  p-channel device with the substrate connected to the source, and the ramp slope has to be changed from falling to rising, as shown in Fig. 9. In this paper, a n-channel version of the comparator with the falling ramp is presented which is more preferred in the image sensor applications. With the falling ramp, the time needed for A/D conversion of a dark signal can be shortened because this signal corresponds to a high voltage V sense . This is important for correlated double sampling (CDS) because it reduces the time interval between signal samples [13].

Random Input Offset Voltage (V os ) and Temporal Noise
A random input offset voltage (V os ) of the comparator in a slope ADC from Fig. 1b is one of the factors leading to the lower image quality. Due to a random V os , the ADC conversion characteristic differs from pixel to pixel resulting in an imaging array nonuniformity and fixed pattern noise (FPN).
The largest impact on V os has the mismatch of M comp . In a first-order approximation, V os is equal to a random deviation of the threshold voltage of M comp . Accurate analysis of the mismatch will not be carried out here. Examples of Operating conditions: V DD = 1.8 V, C load = 50 fF, T ramp = 1 ms a Assuming a full-scale operation range of 0-V DD such analysis for analog comparators can be found in [6,14]. The estimated value of V os based on the simulations is below ±10 mV (1 sigma) for all comparators from Fig. 3. The simulations were based on statistical models developed by the technology provider. The temporal noise in a low-frequency range (1/ f noise) also results in FPN of an image. Fortunately, FPN related to the V os and 1/ f noise can be effectively reduced by 1 to 2 orders of magnitude by CDS [12,13]. Temporal noise in a higher-frequency range causes the jitter at a comparator output, which cannot be removed by CDS. For the comparators from Fig. 3, this noise-induced jitter is below ±0.08 μs (1 sigma) assuming the noise bandwidth of 100 Hz to 10 MHz. Thus, an input-referred noise of the comparators is about 200 μV rms . The results are obtained from the time-domain noise analysis (transient noise analysis) in Cadence Spectre simulator.

Summary of Simulation Results
The major parameters of the comparators from Fig. 3 are summarized in Table 2. They are determined for typical operating conditions: a supply voltage of 1.8 V, a capacitance load of 50 fF, and a ramp time of 1 ms. The corresponding parameters for the lower supply voltage and larger C load , together with the comparison to other solutions, are summarized in Table 3.

Comparison
The proposed comparator was compared to the classic topologies from Fig. 2a, b. To facilitate this comparison, a specific application was selected. It was assumed that the  Fig. 2b are slightly different because this topology must sample the ramp signal at a speed of at least 1 Msample/s (i.e., the frequency on the node "clk" should be at least 1 MHz). This comparator changes its state twice (latch and regeneration) in 1 μs. As a result, the output SR must be doubled, i.e., SR > 2·V DD [V/μs].
For both classic comparators from Fig. 2, optimization of the slew rate and energy consumption was carried out, analogously to that previously done for the proposed comparators. Dimensions of the transistors were chosen such to result in a similar chip surface for all topologies. For the continuous-time comparator, the bias current I bias was set to 50 nA. The most important simulated parameters of all comparators are summarized in Table 3.
The highest SR value was obtained for the dynamic comparator from Fig. 2b. Its SR is 1-2 orders of magnitude higher compared to other comparators due to the built-in positive feedback. However, with the supply reduced to 1 V and for C load increased to 500 fF, its SR drops drastically and the comparator is not able to operate with the required clock frequency of 1 MHz. The continuous-time comparator from Fig. 2a also does not maintain the required speed because its SR falls below the required value 1 V/μs. With the reduced supply voltage and increased load, only the four-stage comparator from Fig. 3c preserves the desired SR.
As opposed to the classical comparators, the proposed topologies allow wider operation range for V sense , specifically for the lower-end values.
With regard to energy consumption per single conversion cycle of a slope ADC, the proposed comparators outperform their classical counterparts. They require 500 times less energy on average than the other comparators. It should be noted that the classical two-stage dynamic comparator from Fig. 2b requires small energy (0.19 pJ) per single-state transition. This amount is similar to the energy consumed by the proposed two-stage comparator from Fig. 3a which is 0.18 pJ. However, the classical comparator must change its state 1000 times during a single A/D conversion cycle resulting in a total energy consumption of 190 pJ, which is similar to that obtained for the continuous-time comparator (140 pJ).

Conclusions
The proposed comparator shows a set of properties adequate for applications in CMOS image sensors, such as low energy consumption (0.5 pJ), small area (25-45 μm 2 ), wide range of input voltage (0.2-1.8 V), and simple design requiring no bias signals or additional power-down mechanisms. In contrast to conventional solutions, the proposed comparator can operate at a supply voltage (1 V) reduced to almost half of its nominal value (1.8 V). This feature makes it attractive also for applications other than image sensors, especially for low-voltage and low-power systems.