Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

1Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh 2Department of Electrical and Electronic Engineering, East West University, Dhaka-1212, Bangladesh *Corresponding author. Email: kalam@ewubd.edu Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors Sishir Bhowmick1 and Khairul Alam2,*

Scaling the transistor sizes has made significant improvement in the cost effectiveness and performance of integrated circuit over the last few decades. The bulk CMOS technology is rapidly approaching the scaling limit and alternate materials or device structures are essential for future electronics. One dimensional nanostructures such as the carbon nanotubes and silicon nanowires are the attractive materials for future nanoelectronics because their electronic properties can be controlled in a predictable manner. Controlled growth of silicon nanowires down to 3 nm diameter [1], their applications as field-effect transistors (FETs) [2][3][4][5], logic gates [6] and sensors [7] have been demonstrated.
When the transistors are scaled to nanometer regime, the device performance degrades mainly due to the short channel effects. The scaling of bulk silicon MOSFETs has been facilitated by introducing the device structures with source-drain underlaps [8]. However, large underlaps are required for optimal performance of bulk MOSFETs [9]. The ultra-thin body or FinFETs with undoped channels and bias dependent effective channel lengths have been proposed for optimal device performance [10,11]. Source-drain underlaps have been used to improve the device performance for carbon nanotube transistors [12,13] and silicon nanowire field-effect transistors (SiNWFETs) [14]. Shin uses multiple gates SiNWFETs and studies the subthreshold behaviors with source-drain underlaps [14].
In this paper, we study the effects of source-drain underlaps on device performance, namely the off current, the on current, the inverse subthreshold slope, S, the gate capacitance, C g , the intrinsic switching delay,  S , and the intrinsic cut-off frequency, f T , of a top gate silicon nanowire on insulator transistor by selfconsistently solving the Poisson's and Schrodinger's equations.
The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with source-drain underlaps. The physics behind this behavior is Doi: 10.5101/nml.v2i2.p83-88 http://www.nmletters.org the modulation of a tunnel barrier by the source-drain underlap.
The source-drain underlaps reduce the gate capacitance that should improve the switching performance of the device.
However, the transconductance and the on current degrade with underlap and the consequence is the reduction of intrinsic cut-off frequency and increase of switching delay.

DEVICE STRUCTURE
Details of the device shown in Fig. 1 are as follows. The silicon nanowire is placed on a thick oxide layer t ox-sub . The gate oxide t ox is grown on the nanowire. A gate metal of length L g is deposited on gate oxide and the exposed regions on both sides of the gate metal are covered by oxide t ox-ex . The nanowire under the gate region and the underlaps L u between the gate and the n-type doped source and drain extension L ex are undoped. The gate length L g is 10 nm and the gate oxide thickness t ox is 1 nm. The silicon nanowire used in our study has a square cross-section of 5 × 5 nm 2 . The substrate oxide, the gate oxide, and the extended oxide are SiO 2 with a dielectric constant value of 3.9. The source Fermi level is set to zero (0) and the drain Fermi level to -qV DS .
The gate metal is assumed to have the same work function value as the nanowire has. The L ex value of 20 nm, the t ox-sub value of 5 nm, and the t ox-ex value of 5 nm are used for Poisson solver so that the fringing electric fields are treated correctly.

SIMULATION MODEL
where ε 0 is the free space permittivity, ε is the relative dielectric constant, V is the 3D potential, and ρ is the charge density, which is non-zero in silicon nanowire only. Poisson kernel is created by discretizing Eq. (1) using finite difference. The normal component of electric field is set to zero at the source and drain ends and at the exposed surface of dielectric. Potential is fixed at the gate metal.
The Schrodinger's equation in 3D cartesian coordinates is where ψ is the wave function, m x , m y , and m z are the effective masses in device coordinates, and ħ is the reduced Planck's constant. The nanowire is grown in <100> direction, which is device x coordinate in our study. Ballistic transport is assumed and recursive Green's function algorithm (RGFA) [15] is used to Hamiltonian H i and layer-to-layer coupling matrix t, we create the right-connected Green function at each layer (cross-section) where U i is the potential energy at the i th cross-section (layer) obtained from Poisson solver and I is the identity matrix. We discretize Schrodinger's equation with equal grid spacing, and therefore, H i is same at each cross-section and t i,i+1 = t and t i+1,i = t † . The full Green's function at the first layer is calculated from where  S =t 1,0 g 0,0 t 0,1 is the self-energy matrix and g 0,0 is the surface Green's function. The surface Green's function is calculated from the decimation method and Ref. [16] has a detailed discussion. The rest {2, …, N x } block diagonal elements of the full Green's function are calculated from , , , We calculate the first column blocks of full Green's function is the broadening function. The charge density at each cross-section is calculated from where q is the electronic charge, f S and f D are the source and drain Fermi functions, respectively, and the full spectral function is The factor 2 at the beginning of right hand side of Eq. (8) includes spin degeneracy. Note that the charge density ρ i,i is a column vector of length N y × N z and is created by taking the diagonal elements of the matrix in the brace of the right hand side of Eq. (8).
The self-consistent loop is started with an initial guess of the potential profile. To generate the initial band profile, we calculate the conduction band position, E CS , relative to the source Fermi level from charge neutrality. The band profile under the gate region is raised by E g /2 (the channel is intrinsic) and that in the drain region is lowered by qV DS . In other word, the initial profile is a step profile with E CS in the source region, E CS +E g /2 under the gate region, and E CS -qV DS in the drain region.
Anderson mixing [17] scheme is used for convergence acceleration. Once the convergence is achieved, the coherent drain current is calculated from where transmission coefficient T(E) is calculated from [15]       .
The calculation is performed for each valley, and the charge density and drain current are obtained by taking sum over the valleys.

SIMULATION RESULTS
The silicon nanowire on insulator device used in our simulation is shown in Fig. 1. The channel consists of an undoped silicon nanowire of square cross-section of 5 × 5 nm 2 . A 20 nm doped source-drain extension (L ex ) with a doping concentration value of 2×10 19 cm -3 is assumed in our simulation.
The nanowire is modeled using bulk effective mass parabolic band structure. Using the tight binding (TB) dispersion relation and the bulk effective mass model, Wang et al. [18] argued, using a semiclassical over the top of the barrier model, that the bulk effective mass model overestimates the threshold voltage for wire width < 3 nm and the on current for wire width < 5 nm.
Using sp 3 d 5 s * orbital basis, Zheng et al. [19] show that the bulk masses are quite similar to the confinement masses for wire thickness greater than 3 nm. Shin [14,20]  for gate-all-around and tri-gate silicon nanowire transistors have been reported by Shin [14]. The off-state current in both types of gate structure improves by four orders of magnitude or higher when the underlap is changed from 0 to 5 nm. The inverse subthreshold slope in their [14] gate-all-around transistors is ≈ 135 mV/dec at no underlap. This value improves to below 100 mV/dec at an underlap of 5 nm.
Note that the on/off current ratio of 9. Next we study the effects of source-drain underlaps on the gate capacitance, the intrinsic switching delay, and the intrinsic cut-off frequency. For this, the gate capacitance is calculated where, the first integral takes care of the electric fluxes emanating from the bottom surface of the gate metal and the second integral takes care of the fringing fields emanating from the two sides of the gate metal facing to the source and drain. The intrinsic switching delay is calculated from  S = C g V DD /I on and the intrinsic cut-off frequency from f T =g m /2C g . The transconductance is calculated from g m =I D /V GS .
The gate capacitance values and the percentage contribution of its different components versus gate bias are shown in Fig. 6.
Here C b is corresponding to the contribution from the fluxes emanating from the bottom surface of the gate metal and is evaluated by the first integral of Eq. (11), and C s and C d are the fringing field contributions emanating from the left side of the gate metal to the source, and from the right side of the gate metal to the drain, respectively, and are evaluated from the second integral of Eq. (11). The major contribution comes from C b and its value ranges from 45% to 51%. The rest, which is almost 50% of the contribution of gate capacitance comes from the fringing fields.
In Fig. 7, we plot the gate capacitance and its different components (C b , C s , and C d ), the transconductance, the switching delay, and the intrinsic cut-off frequency as a function of underlap. The gate capacitance reduces with underlap that should reduce the switching delay. However, the on current also reduces with underlap, and the combined effect is increase of the switching delay. The reduction of g m with underlap should reduce f T and the reduction of C g with underlap should increase f T . However, the reduction rate of g m is higher and the consequence is the reduction of f T . The gate capacitance, the