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PM-Migration: A Page Placement Mechanism for Real-Time Systems with Hybrid Memory Architecture

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Algorithms and Architectures for Parallel Processing (ICA3PP 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14491))

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Abstract

Due to its higher storage density and lower energy consumption compared to DRAM, persistent memory (PM) holds the potential to address the growing memory demands of applications, such as Deep Neural Network (DNN) training. However, PM also suffers from longer latency and lower bandwidth, making it impractical to completely replace DRAM. The hybrid memory architecture, which combines DRAM and PM, is expected to improve this issue. Nevertheless, it also introduces a challenging problem: the state-of-the-art page placement mechanism designed for DRAM-only systems with NUMA ignores the performance disparities between DRAM and PM, resulting in sub-optimal performance. To improve this problem, we propose PM-Migration, a page placement mechanism tailored for real-time systems with hybrid memory architecture. PM-Migration prioritizes placing frequently accessed pages in DRAM and increases the access frequency of write-intensive pages to leverage the read-write asymmetry of Intel Optane DC persistent memory module (DCPMM), a commercially available PM hardware. It also incorporates a transmission handover strategy to select the transfer engine according to the size of the page and then utilizes DMA technology for migrating pages of size 2 MB. Experimental results demonstrate that PM-Migration provides an average throughput improvement of 1.31\(\times \) to 3.6\(\times \) compared to existing mechanisms proposed for the hybrid memory architecture.

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Acknowledgment

This work was funded by the Key-Area Research and Development Program of Guangdong Province under grant number 2020B0101650001, by the National Natural Science Foundation of China under grant number 61972164.

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Correspondence to Dingding Li .

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Xu, L., Chen, G., Li, D., Luo, H. (2024). PM-Migration: A Page Placement Mechanism for Real-Time Systems with Hybrid Memory Architecture. In: Tari, Z., Li, K., Wu, H. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2023. Lecture Notes in Computer Science, vol 14491. Springer, Singapore. https://doi.org/10.1007/978-981-97-0808-6_18

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  • DOI: https://doi.org/10.1007/978-981-97-0808-6_18

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  • Online ISBN: 978-981-97-0808-6

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