Abstract
Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction of an 8-, 16-, 32-, 64-bit multiplier using the carry-save adder, the Kogge stone adder, and the HNFG adder with the high operating speed of the proposed HNFG gate adder. The architecture of the device and the logic gates which are reversible can be implemented using the Vedic multiplier. The output of the accumulator operation is dependent on the multiplier unit and the adder units. Here, the development of a multiplier and an adder can be built using reversible gates to achieve high operating speeds, and the use of a Vedic multiplier for greater efficiency. Also fewer area and partial elements are used. A comparative study is being conducted between the conventional [1] and the Kogge stone adder based on HNFG. Finally, it has been shown that the proposed HNFG gate with multiplier adder has a relatively high-speed over the conventional method. The whole process of simulation and synthesis is done using Xilinx 14.7 tool.
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Yuvaraj, S.A., Gunasekaran, K., Muthukumaran, D., Umapathy, K. (2021). FPGA Implementation of Parallel Adder Using Reversible Logic Gates. In: Sharma, D.K., Son, L.H., Sharma, R., Cengiz, K. (eds) Micro-Electronics and Telecommunication Engineering. Lecture Notes in Networks and Systems, vol 179. Springer, Singapore. https://doi.org/10.1007/978-981-33-4687-1_40
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