Abstract
Communication is among the vast and fast-growing engineering fields. Improving communication efficiency by overcoming external electromagnetic and noise sources is a difficult task. Different methods for detecting and resolving errors are implemented to reduce data loss during transmission. A novel approach that uses cyclic redundancy tests is proposed in this paper. In the field of communication, there have been many developments in the digital world. In most fields of communication, the input message or data is encoded and transmitted through a medium of transmission. Data are obtained at the receiver and the original data is successfully retrieved after decoding the received data. The paper aims to explain the hammer code design cycle with VLSI, as FPGA is cheaper than the other device. The hamming algorithm for encoding and decoding was discussed in this paper and the results were obtained by implementing hamming error detection and the correction code. Compared to the traditional Narayanan and Ramesh (Journal of Engineering and Applied Sciences 12:6281–6285, 2017 [1]) hamming parity checking process, hamming code is an improved version and used in Verilog to transmit n-bit information with redundancy bits. A hamming to find out how important these redundant bits.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Narayanan KL, Ramesh GP (2017) VLSI Architecture for multi-band wavelet transform based image compression and image reconstruction. J Eng Appl Sci 12:6281–6285
Forouzan AB (2007) Data communications and networking (sie), Tata McGraw-Hill Education
Parvez M, Shahariar AHM et al. (2019) Design and implementation of hamming encoder and decoder over FPGA. In: International conference on computer networks and communication technologies, Springer, Singapore
Pedroni VA (2008) In: Digital electronics and design with VHDL, Morgan Kaufmann
Berrou C, Glavieux A (1996) Near optimum error correcting coding and decoding: turbo-codes. IEEE Trans Commun 44.10:1261–1271
Gross WJ, Kschischang FR, Koetter R, Gulak PG (2006) Applications of algebraic soft-decision decoding of Reed-Solomon codes. IEEE Trans Commun 54(7):1224–1234
Ashenden PJ (2007) In: Digital design (verilog): An embedded systems approach using verilog, Elsevier
Panda AK, Sarik S, Awasthi A (2012) FPGA implementation of encoder for (15, k) binary BCH code using VHDL and performance comparison for multiple error correction control. In: 2012 International conference on communication systems and network technologies, IEEE, pp 780–784
Goss Y, Paul E, Strasser-Weippl K, Lee-Bychkovsky BL, Fan L, Li J, Chavarri-Guerra Y, Pedro ERL et al (2014) Challenges to effective cancer control in China, India, and Russia. Lancet Oncol 15(5):489–538
Cohen DB (2002) Real chip design and verification using verilog and VHDL, vhdlcohen publishing
Ramesh GP (2020) Design of digital FIR filters for low power applications. In: Intelligent computing in engineering, Springer, Singapore, pp 433–440
Podder P, Hasan MM, Khan TZ (2014) FPGA implementation of high performance fast page mode dynamic random access memory. In: The 8th international conference on software, knowledge, information management and applications (SKIMA 2014), IEEE, pp 1–7
Mathew B, Neepa P, Anith M (2016) Matrix code based error correction for LUT based cyclic redundancy check. Proc Technol 25:590–597
Paul A, Khan TZ, Podder P, Hasan MM, Ahmed T (2015) Reconfigurable architecture design of FIR and IIR in FPGA. In: 2015 2nd International conference on signal processing and integrated networks (SPIN), IEEE, pp 958–963
Shamir MA, Safran I, Ronen E, Dunkelman O (2019) A simple explanation for the existence of adversarial examples with small hamming distance. arXiv preprint arXiv:1901.10861
Rajavelu T (2012) Implementation of umhexagons motion estimation algorithm for video coding standard. Int J MC Square Sci Res 4(1):42–47
Pedroni VA (2008) In: Digital electronics and design with VHDL, Morgan Kaufmann
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Umapathy, K., Yuvaraj, S.A., Gunasekaran, K., Muthukumaran, D. (2021). FPGA Based Implementation of Hamming Encoder and Decoder. In: Sharma, D.K., Son, L.H., Sharma, R., Cengiz, K. (eds) Micro-Electronics and Telecommunication Engineering. Lecture Notes in Networks and Systems, vol 179. Springer, Singapore. https://doi.org/10.1007/978-981-33-4687-1_24
Download citation
DOI: https://doi.org/10.1007/978-981-33-4687-1_24
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-33-4686-4
Online ISBN: 978-981-33-4687-1
eBook Packages: EngineeringEngineering (R0)