Abstract
At present, more than half the chip area is occupied by memory. So, it becomes imperative to find an efficient design of memory and deal with issues of power, delay, and reliability. A significant amount of memory delay is caused by its decoder. The optimized decoder used in this paper is faster than the conventional decoder by approximately 80% and consumes 92% lesser power. In this paper, four types of decoders are discussed with their performance comparison. A pre-charge pulse generator is also used in the design to pull up the bit-lines before performing the read operation. This paper aims to provide the optimal design of static random-access memory (SRAM) and an efficient address decoder. In the quest for efficient design, the focus remains on reducing total transistor counts and their optimum sizing.
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Kulshrestha, A., Samaiya, S., Jha, O.N., Saini, G. (2022). Design of High Speed and Power Efficient 16 × 8 SRAM Memory Using Improved 4 × 16 Decoder. In: Lenka, T.R., Misra, D., Biswas, A. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 781. Springer, Singapore. https://doi.org/10.1007/978-981-16-3767-4_14
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DOI: https://doi.org/10.1007/978-981-16-3767-4_14
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