Enhanced Static Secure Logic for Hardware Security

Abstract

As the electronic activity is penetrating into various situations of life like electronic governance, banking and reservation systems, the need for higher and higher security in protecting the banking transactions, passwords, PNR numbers, etc. is increasing. The security lapses occur through both software and hardware. The side channel attacks (SCAs) use the details of power pattern, timing details and leakage information. Differential Power Analysis (DPA) attack is also a major threat, where the intruder analyzes the fluctuations in the power consumption to estimate the secret key of the implemented encryption algorithm in the IC as security. As a remedy, logic gates having constant power dissipation that are not dependent on input signals are used in security ICs, i.e., for every input pattern, consumed power and circuit characteristics like identical leakage current, instantaneous current, input–output delay, independent of logic value and sequence of input data. Implementation of the encryption module inside logic will protect the device against side channel attacks. This paper aims at developing an Enhanced Static Secure Logic (ESSL) for basic circuits required for implementing a larger module. They are compared for area, power consumption and variations in power consumption against Static Complementary CMOS logic, genuine Dynamic and Differential Logic.