Abstract
With the advancement of sensors and network-enabled devices, the need for high performance and low power consumption is increasing day by day. The major delaying part of these devices is the multipliers built into the digital filters for performing signal processing applications. This paper proposes a design of various conventional and traditional multiplier algorithms to design finite impulse response (FIR) filter of order four, eight, sixteen, thirty two and sixty four and its performance analysis in terms of delay, memory usage and level of logic used.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
G.G. Kumar, S.K. Sahoo, Implementation of a high speed multiplier for high performance and low power applications, in Proceedings of the IEEE 19th International Symposium on VLSI Design and Test (VDAT) (2015), pp. 1–4
V. Sharma, A. Kumar, Design, implementation & performance of vedic multiplier for different bit lengths. Int. J. Innovative Res. Comput. Commun. Eng. 5(4), 7912–7919 (2017). ISSN: 2320-9801(O), 2320-9798(P)
A. Kumar, V. Sharma, Comparative analysis of vedic & array multiplier. Int. J. Electron. Commun. Eng. Technol. 8(3), 17–27 (2017). ISSN: 0976-6464 (P), 0976-6472
A. Kumar, E. Gupta, R.A. Shobhit, R.K. Jain, Comparative research for managing delay in signal processing via multipliers, in Proceedings of 2nd IEEE International Conference on Power Electronics, Intelligent control and energy Systems (ICPIECES-2018), DTU, India (2018), pp. 1549–1554. ISBN: 978-1-5386-6626-5
A. Kumar, R.P. Agarwal, An approach to manage delay in signal processing via selected multiplier algorithms, in Proceedings of 3rd IEEE International Conference on Inventive Computation Technologies (3rd ICICT 2018) Conference Proceedings, RVS Technical Campus, Coimbatore, Tamil Nadu, India (2018), pp. 401–405. ISBN: 978-1-5386-4985-5
A. Kumar, R.P. Agarwal, Simulation & implementation of efficient multiplier circuits, in Proceedings of 2nd International Conference on Recent Multidisciplinary Research (ICRMR-2018), Asian Institute of Technology Conference Centre, Thailand, 23–24 November 2018, pp. 1–6. Published in Online Int. Interdisc. Res. J. (OIIRJ) 8(2), 104–111 (2018). ISSN: 2249-9598. UGC J. No. 46964
A. Kumar, R.P. Agarwal, Complex multiplier: implementation using efficient algorithms for signal processing application. Int. J. Recent Technol. Eng. 8, 1235–1239 (2019). ISSN: 2277-3878, UGC J. No. 49239
A. Kumar, R.P. Agarwal, Delay estimation, area analyses and comparison of digital multiplier techniques for signal processing applications, in Proceedings of International Webinar (e-conference) on “Prospective of Interdisciplinary Research in Science and Technology in Present Scenario”, Department of Physics, CCSU, Meerut (2020)
D. Behera, A. Patnaik, P.K. Barik, G.S. Rath, VLSI implementation of digital filter using novel RTSD adder and booth multiplier. Int. J. Eng. Adv. Technol. 9, 4131–4139 (2020)
R. Shetty, M.B. Neelagar, Design and implementation of high performance 4-bit dadda multiplier using compressor. Int. J. Comput. Sci. Mobile Comput. 6(7), 249–254 (2017)
P.K. Sinha, P. Sharan, multiplexer based multiplications for signal processing applications. Indonesian J. Electr. Eng. Comput. Sci. 9(3), 583–586 (2018)
A.S. Thakur, V. Tiwari, Design high speed FIR filter based on complex vedic multiplier using CBL adder, in 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE), Bhubaneswar, India (2018), pp. 559–563
M. Tiwari, A. Kumar, Implementation of high speed and low power novel radix 2 booth multiplier using 2248 BEC converter. Int. J. Eng. Sci. Comput. 7, 4861–4863 (2017). ISSN 2321 3361
A. Kumar, M. Tiwari, Simulation, implementation & comparative analysis of multiplier, in Proceedings of International Conference on Recent Trends in Operations Research & Statistics (RTORS-2017), IIT Roorkee, India (2017), pp. 29, 28–30
E. Gupta, A. Kumar, R.K. Jain, Simulation & comparative analysis of booth multiplier. Int. J. Electron. Eng. 10(2), 404–412 (2018). ISSN: 0973-7383, UGC J. No. 2946
A. Mittal, A. Nandi, D. Yadav, Comparative study of 16-order FIR filter design using different multiplication techniques. IET Circ. Devices Syst. 11, 196–200 (2017)
Mamta, A. Kumar, Comparative analysis of FIR filter. Int. J. Adv. Eng. Res. Dev. 3, 88–95 (2016). ISSN 2348-4470(O), 2348-6406(P)
S. Soundarya, N. Arumugam, R. Rameshkumar, Design of FIR filter using efficient adder and multiplier for ECG signal processing applications. Int. J. Eng. Appl. Sci. Technol. 2020(4), 276–282 (2020)
R.A. Sekar, S. Sasipriya, Implementation of FIR filter using reversible modified carry select adder, in Special Issue: Recent Research Challenges in Intelligent Techniques, Big Data and Internet of Things, vol. 31 (2019), pp. 1–9
A. Kumar, Mamta, Comparison of different types of IIR filters. Int. J. Adv. Res. Electron. Commun. Eng. 5(2), 393–402 (2016). ISSN: 2278-909X
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Kumar, A., Agarwal, R.P. (2021). Performance Evaluation and Synthesis of FIR Filters Using Various Multipliers Algorithms. In: Mekhilef, S., Favorskaya, M., Pandey, R.K., Shaw, R.N. (eds) Innovations in Electrical and Electronic Engineering. Lecture Notes in Electrical Engineering, vol 756. Springer, Singapore. https://doi.org/10.1007/978-981-16-0749-3_45
Download citation
DOI: https://doi.org/10.1007/978-981-16-0749-3_45
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-0748-6
Online ISBN: 978-981-16-0749-3
eBook Packages: EnergyEnergy (R0)