Zusammenfassung
We present a hard real-time memory management system which achieves a worst-case complexity of \(\mathcal{O}\)(1) for traditional single-cell operations as well as for selected multi-cell operations. On FPGAs, execution time decreases to a single clock cycle per operation.
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© 2021 Der/die Autor(en), exklusiv lizenziert durch Springer Fachmedien Wiesbaden GmbH, ein Teil von Springer Nature
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Lohmann, S., Tutsch, D. (2021). Hard Real-Time Memory-Management in a Single Clock Cycle (on FPGAs). In: Unger, H. (eds) Echtzeit 2020. Informatik aktuell. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-32818-4_4
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DOI: https://doi.org/10.1007/978-3-658-32818-4_4
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