Skip to main content

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 53))

Abstract

The chapter discussed contemporary field-programmable logic devices and their evolution, starting from the simplest programmable logic devices such as PROM, PLA, PAL and GAL, and finishing with very sophisticated chips such as CPLD and FPGA. This analysis shows particular features of different logic elements and permits to optimize the FSM logic circuits, in which some particular elements are used. The analysis is accompanied by some examples for systems of Boolean functions implementation using PROM, PLA and PAL chips. The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Adamski, M., Barkalov, A.: Architectural and Sequential Synthesis of Digital Devices. University of Zielona Góra Press, Zielona Góra (2006)

    Google Scholar 

  2. Altera Corporation Webpage, http://www.altera.com

  3. Asahar, P., Devidas, S., Newton, A.: Sequential Logic Synthesis. Kluwer Academic Publishers, Boston (1992)

    Google Scholar 

  4. Atmel Corporation Webpage, http://www.atmel.com

  5. Baranov, S.: Logic and System Design of Digital Systems. TUT Press, Tallinn (2008)

    Google Scholar 

  6. Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers, Dordrecht (1994)

    Google Scholar 

  7. Barkalov, A.: Multilevel pla schemes for microprogram automata. Cybernetics and system analysis 31(4), 489–495 (1995)

    Google Scholar 

  8. Barkalov, A., Beleckij, O., Nedal, A.: Applying of optimization methods of moore automaton for synthesis of compositional microprogram control unit. Automatic Control and Computer Sciences 33(1), 44–52 (1999)

    Google Scholar 

  9. Barkalov, A., Dzhaliashvili, Z., Salomatin, V., Starodubov, K.: Optimization of a microinstruction address scheme for microprogram control unit with pla and prom. Automatic Control and Computer Sciences 20(5), 83–87 (1986)

    Google Scholar 

  10. Barkalov, A., Kołopieńczyk, M., Titarenko, L.: Optimization of control memory size of control unit with codes sharing. In: Proc. of the IXth Inter. Conf. CADSM 2007, pp. 242–245. Lviv Polytechnic National University, Publishing House of Lviv Polytechnic National University, Lviv (2007)

    Google Scholar 

  11. Barkalov, A., Salomatin, V., Starodubov, K., Das, K.: Optimization of mealy automaton logic using programmable logic arrays. Cybernetics and system analysis 27(5), 789–793 (1991)

    Article  Google Scholar 

  12. Barkalov, A., Titarenko, L.: Logic Synthesis for Compositional Microprogram Control Units. Springer, Berlin (2008)

    Book  MATH  Google Scholar 

  13. Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH, Donetsk (2009)

    Google Scholar 

  14. Barkalov, A., Titarenko, L., Barkalov Jr., A.: Moore fsm synthesis with coding of compatible microoperations fields. In: Proc. of IEEE East-West Design & Test Symposium - EWDTS 2007, Yerevan, Armenia, pp. 644–646. Kharkov National University of Radioelectronics, Kharkov (2007)

    Google Scholar 

  15. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of logic circuit of moore fsm on CPLD. Pomiary Automatyka Kontrola 53(5), 18–20 (2007)

    Google Scholar 

  16. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on CPLD. In: Proceedings of the Sixth Inter. conf. CAD DD 2007, Minsk, vol. 2, pp. 39–45 (2007)

    Google Scholar 

  17. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on CPLD. International Journal of Applied Mathematics and Computer Science 17(4), 565–675 (2007)

    Article  MathSciNet  Google Scholar 

  18. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on system-on chip. In: Proc. of IEEE East-West Design & Test Symposium – EWDTS 2007 (2007)

    Google Scholar 

  19. Barkalov, A., Titarenko, L., Chmielewski, S.: Decrease of hardware amount in logic circuit of moore fsm. Przeglźd Telekomunikacyjny i Wiadomości Telokomunikacyjne (6), 750–752 (2008)

    Google Scholar 

  20. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore control unit with refined state encoding. In: Proc. of the 15th Inter. Conf. MIXDES 2008, Poznań, Poland, pp. 417–420. Departament of Microeletronics and Computer Science, Technical University of Łódz (2008)

    Google Scholar 

  21. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on system-on-chip using pal technology. In: Proc. of the International Conference TCSET 2008, Lviv-Slavsko, Ukraina, pp. 314–317. Ministry of Education and Science of Ukraine, Lviv Polytechnic National University, Publishing House of Lviv Polytechnic, Lviv (2008)

    Google Scholar 

  22. Barkalov, A., Titarenko, L., Kołopieńczyk, M.: Optimization of circuit of control unit with code sharing. In: Proc. of IEEE East-West Design & Test Workshop - EWDTW 2006, Sochi, Rosja, pp. 171–174. Kharkov National University of Radioelectronics, Kharkov (2006)

    Google Scholar 

  23. Barkalov, A., Titarenko, L., Kołopieńczyk, M.: Optimization of control unit with code sharing. In: Proc. of the 3rd IFAC Workshop: DESDES 2006, Rydzyna, Polska, pp. 195–200. University of Zielona Góra Press, Zielona Góra (2006)

    Google Scholar 

  24. Barkalov, A., Wiśniewski, R.: Optimization of compositional microprogram control unit with elementary operational linear chains. Upravlauscie Sistemy i Masiny (5), 25–29 (2004)

    Google Scholar 

  25. Barkalov, A., Wiśniewski, R.: Optimization of compositional microprogram control units with sharing of codes. In: Proc. of the Fifth Inter. Conf. CADD’DD 2004, Minsk, Belorus, vol. 1, pp. 16–22. United Institute of the Problems of Informatics, Minsk (2004)

    Google Scholar 

  26. Barkalov, A., Wiśniewski, R.: Design of compositional microprogram control units with maximal encoding of inputs. Radioelektronika i Informatika (3), 79–81 (2004)

    Google Scholar 

  27. Barkalov, A., Węgrzyn, M.: Design of Control Units With Programmable Logic. University of Zielona Góra Press, Zielona Góra (2006)

    Google Scholar 

  28. Barkalov, A., Wêgrzyn, A., Barkalov Jr., A.: Synthesis of control units with transformation of the codes of objects. In: Proc. of the IXth Inter. Conf. CADSM 2007, Lviv - Polyana, Ukraine, pp. 260–261. Lviv Polytechnic National University, Publishing House of Lviv Polytechnic National University, Lviv (2007)

    Google Scholar 

  29. Barkalov, A.A., Wêgrzyn, M., Wiśniewski, R.: Partial reconfiguration of compositional microprogram control units implemented on fpgas. In: Proceedings of IFAC Workshop on Programmable Devices and Embedded Systems (Brno), pp. 116–119 (2006)

    Google Scholar 

  30. Barkalov, A.A.: Microprogram control unit as composition of automate with programmable and hardwired logic. Automatics and computer technique (4), 36–41 (1983) (in Russian)

    Google Scholar 

  31. Barkalov, A.A., Titarenko, L.A.: Design of control units with programmable logic devices. In: Korbicz, J. (ed.) Measurements, methods, systems and design, pp. 371–391. Wydawnictwo Komunikacji i Łączności, Warsaw (2007)

    Google Scholar 

  32. Barkalov, A.A., Wiśniewski, R.: Optimization of compositional microprogram control units implemented on system-on-chip. Theoretical and applied informatics (9), 7–22 (2005)

    Google Scholar 

  33. Borowik, G.: Synthesis of sequential devices into FPGA with embedded memory blocks. PhD thesis. WUT, Warszawa (2007)

    Google Scholar 

  34. Brayton, R., Rudell, R., Sangiovanni-Vincentelli, A., Wang, A.: MIS: a multi- level logic optimization system. IEEE Transactions on Computer-Aided Design 6, 1062–1081 (1987)

    Article  Google Scholar 

  35. Brown, S., Vernesic, Z.: Fundamentals of Digital Logic with VHDL Design. McGraw-Hill, New York (2000)

    Google Scholar 

  36. Brown, S., Vernesic, Z.: Fundamentals of Digital Logic with Verilog Design. McGraw-Hill, New York (2003)

    Google Scholar 

  37. Bukowiec, A.: Synthesis of Finite State Machines for Programmable devices based on multi-level implementation. PhD thesis, University of Zielona Góra (2008)

    Google Scholar 

  38. Chu, P.: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability and Scalability. Wiley-Interscience, Hoboken (2006)

    Book  Google Scholar 

  39. Cypress Programmable Logic: Delta 39K. Data Sheet, http://cypress.com/pld/delta39k.html

  40. Cypress Semiconductor Corporation, http://www.cypress.com

  41. Czerwinski, R., Kania, D.: State assignment method for high speed FSM. In: Proc. of Programmable Devices and Systems, pp. 216–221 (2004)

    Google Scholar 

  42. Czerwinski, R., Kania, D.: State assignment for PAL-based CPLDs. In: Proc. of 8th Euromicro Sym. on Digital System Design, pp. 127–134 (2005)

    Google Scholar 

  43. Debnath, D., Sasao, T.: Multiple-valued minimization to optimize PLA with output EXOR gates. In: Proc. of IEEE Inter. Symp. on Multiple-Valued Logic, pp. 99–104 (1999)

    Google Scholar 

  44. Sasao, T., Debnath, D.: Doutput phase optimization for and-or-exor plas with decoders and its application to design of adders. IFICE Transactions on Information and Systems E88-D(7), 1492–1500 (2005)

    Google Scholar 

  45. Devadas, S., Ma, H.: Easily testable PLA-based finite state machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9(6), 604–611 (1990)

    Article  Google Scholar 

  46. Hassoun, S., Sasao, T.: Logic synthesis and verification. Kluwer Academic Publishers, Dordrecht (2002)

    Google Scholar 

  47. Hatchel, G., Somenzi, F.: Logic synthesis and verification algorithms. Kluwer Academic Publishers, Dordrecht (2000)

    Google Scholar 

  48. Hrynkiewicz, E., Kania, D.: Impact of decomposition direction on synthesis effectiveness. In: Proc. of Programmable Devices and Systems (PDS 2003), pp. 144–149 (2003)

    Google Scholar 

  49. Jenkins, J.: Design with FPGAs and CPLDs. Prentice Hall, New York (1995)

    Google Scholar 

  50. Kam, T., Villa, T., Brayton, R., Sangiovanni-Vincentelli, A.: A Synthesis of Finie State Machines: Functional Optimization. Kluwer Academic Publishers, Boston (1998)

    Google Scholar 

  51. Kania, D.: Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition. In: Proc. of 25th Euromicro Conference, pp. 278–281 (1999)

    Google Scholar 

  52. Kania, D.: Two-level logic synthesis on PALs. Electronic Letters (17), 879–880 (1999)

    Google Scholar 

  53. Kania, D.: Coding capacity of PAL-based logic blocks included in CPLDs and FPGAs. In: Proc. of IFAC Workshop on Programmable Devices and Systems (PDS 2000), pp. 164–169. Elseveir Science, Amsterdam (2000)

    Google Scholar 

  54. Kania, D.: Decomposition-based synthesis and its application in PAL-oriented technology mapping. In: Proc. of 26th Euromicro Conference, pp. 138–145. IEEE Computer Society Press, Maastricht (2000)

    Google Scholar 

  55. Kania, D.: An efficient algorithm for output coding in PAL-based CPLDs. International Journal of Engineering [57], 325–328

    Google Scholar 

  56. Kania, D.: An efficient algorithm for output coding in PAL-based CPLDs. International Journal of Engineering [57], 325–328

    Google Scholar 

  57. Kania, D.: An efficient algorithm for output coding in PAL-based CPLDs. International Journal of Engineering 15(4), 325–328 (2002)

    Google Scholar 

  58. Kania, D.: An efficient approach to synthesis of multi-output boolean functions on PAL-based devices. In: IEEE Proc. – Computer and Digital Techniques, vol. 150, pp. 143–149 (2003)

    Google Scholar 

  59. Łuba, T., Jasiński, K., Zbierzchowski, B.: Spcialized digital circuits in PLD i FPGA structures. Wydawnictwo Komunikacji i Łączności (1997) (in Polish)

    Google Scholar 

  60. Łuba, T., Rawski, M., Jachna, Z.: Functional decomposition as a universal method for logic synthesis of digital circuits. In: Proc. of IX Inter. Conf. MIXDES 2002, pp. 285–290 (2002)

    Google Scholar 

  61. Maxfield, C.: The Design Warrior’s Guide to FPGAs. Academic Press, Inc., Orlando (2004)

    Google Scholar 

  62. Maxfield, C.: FPGAs: Instant access. Newnes (2008)

    Google Scholar 

  63. McCluskey, E.: Logic Design Principles. Prentice Hall, Englewood Cliffs (1986)

    Google Scholar 

  64. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)

    Google Scholar 

  65. Minns, P., Elliot, I.: FSM-based digital design using Verilog HDL. John Wiley and Sons, Chichester (2008)

    Book  Google Scholar 

  66. Navabi, Z.: Embedded Core Design with FPGAs. McGraw-Hill, New York (2007)

    Google Scholar 

  67. Papachristou, C.: Hardware microcontrol schemes using PLAs. In: Proceeding of 14th Microprogramming Workshop, vol. 2, pp. 3–15 (1981)

    Google Scholar 

  68. Papachristou, C., Gambhir, S.: A microsequencer architecture with firmware support for modular microprogramming. ACM SIGMICRO Newsletters 13(4) (1982)

    Google Scholar 

  69. Parnel, K., Mechta, N.: Programmable Logic design Quick Start Hand Book. Xilinx (2003)

    Google Scholar 

  70. Patterson, D., Henessy, J.: Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, San Moteo (1998)

    Google Scholar 

  71. Pedroni, V.: Circuit Design with VHDL. MIT Press, Cambridge (2004)

    Google Scholar 

  72. Rawski, M., Luba, T., Jachna, Z., Tomaszewicz, P.: The influence of functional decomposition on modern digital design process. In: Design of Embedded Control Systems, pp. 193–203. Springer, Boston (2005)

    Chapter  Google Scholar 

  73. Rawski, M., Selvaraj, H., Luba, T.: An application of functional decomposition in ROM-based FSM implementation in FPGA devices. Journal of System Architecture 51(6-7), 423–434 (2005)

    Google Scholar 

  74. Salcic, Z.: VHDL and FPLDs in Digital Systems Design, Prototyping and Customization. Kluwer Academic Publishers, Dordrecht (1998)

    MATH  Google Scholar 

  75. Sasao, T.: Switching Theory for Logic Synthesis. Kluwer Academic Publishers, Dordrecht (1999)

    MATH  Google Scholar 

  76. Saucier, G., Depaulet, M., Sicard, P.: ASYL: a rule-based system for controller synthesis. IEEE Transactions on Computer-Aided Design 6(11), 1088–1098 (1987)

    Article  Google Scholar 

  77. Saucier, G., Sicard, P., Bouchet, L.: Multi-level synthesis on programmable devices in the ASYL system. In: Proceedings of Euro ASIC, pp. 136–141 (1990)

    Google Scholar 

  78. Scholl, C.: Functional Decomposition with Application to FPGA Synthesis. Kluwer Academic Publishers, Boston (2001)

    MATH  Google Scholar 

  79. Sentowich, E., Singh, K., Lavango, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Bryton, R., Sangiovanni-Vincentelli, A.: SIS: a system for sequential circuit synthesis. Technical report, University of California, Berkely (1992)

    Google Scholar 

  80. Sentowich, E., Singh, K., Lavango, L., Moon, C., Murgai, R., Saldanha, S., Savoj, H., Stephan, P., Bryton, R., Sangiovanni-Vincentelli, A.: SIS: a system for sequential circuit synthesis. In: Proc. of the Inter. Conf. of Computer Design (ICCD 1992), pp. 328–333 (1992)

    Google Scholar 

  81. Shriver, B., Smith, B.: The anatomy of a High-performance Microprocessor: A Systems Perspective. IEEE Computer Society Press, Los Alamitos (1998)

    Google Scholar 

  82. Solovjev, V., Czyzy, M.: Refined CPLD macrocells architecture for effective FSM implementation. In: Proc. of the 25th EUROMICRO Conference, Milan, Italy, vol. 1, pp. 102–109 (1999)

    Google Scholar 

  83. Solovjev, V., Czyzy, M.: The universal algorithm for fitting targeted unit to complex programmable logic devices. In: Proc. of the 25th EUROMICRO Conference, Milan, Italy, vol. 1, pp. 286–289 (1999)

    Google Scholar 

  84. Solovjev, V.V.: Design of Digital Systems Using the Programmable Logic Integrated Circuits. Hot line – Telecom, Moscow (2001) (in Russian)

    Google Scholar 

  85. Villa, T., Saldachna, T., Brayton, R., Sangiovanni-Vincentelli, A.: Symbolic two-level minimization. IEEE Transactions on Computer-Aided Design 16(7), 692–708 (1997)

    Article  Google Scholar 

  86. Wiśniewski, R.: Synthesis of Compositional Microprogram Control Units for Programmable Devices. PhD thesis, University of Zielona Góra (2008)

    Google Scholar 

  87. Wiśniewski, R., Barkalov, A., Titarenko, L.: Optimization of address circuit of compositional microprogram unit. In: Proc. of IEEE East-West Design & Test Workshop - EWDTW 2006, Sochi, Rosja, pp. 167–170. Kharkov National University of Radioelectronics, Kharkov (2006)

    Google Scholar 

  88. Wiśniewski, R., Barkalov, A., Titarenko, L.: Synthesis of compositional microprogram control units with sharing codes and address decoder. In: Proc. of the Inter. Conf. MIXDES 2006, Gdynia, Polska, pp. 397–400. Departament of Microelectronics and Computer Science, Technical University of Łódz (2006)

    Google Scholar 

  89. Xilinx Corporation Webpage, http://www.xilinx.com

  90. Yang, S.: Logic synthesis and optimization benchmarks user guide. Technical report, Microelectronic Center of North Carolina (1991)

    Google Scholar 

  91. Yanushkevich, S., Shmerko, V.: Introduction to Logic Design. CRC Press, Boca Raton (2008)

    MATH  Google Scholar 

Download references

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Barkalov, A., Titarenko, L. (2009). Evolution of Programmable Logic. In: Logic Synthesis for FSM-Based Control Units. Lecture Notes in Electrical Engineering, vol 53. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04309-3_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-04309-3_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-04308-6

  • Online ISBN: 978-3-642-04309-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics