A High-Speed Barret-Based Modular Multiplication with Bit-Correction for the CRYSTAL-KYBER Cryptosystem

Abstract

The CRYSTAL-Kyber algorithm is the only Public-key Encryption algorithm selected by the National Institute of Standards and Technology (NIST) in the third round of the Post-Quantum Cryptography (PQC) Standardization Process. Hardware architectures for the CRYSTAL-Kyber cryptosystem must be designed to hasten the execution of the operands of cryptographic algorithms, particularly high-order polynomial multiplication. All operands are reduced modularly to produce finite groups, rings, or fields. This paper utilizes an optimized variant of the Barret reduction algorithm, combined with a bit-correction module, to calculate the precision of the estimated quotient q̂. As a result, only one conditional subtraction is required without DSPs. The proposed structure is simulated and synthesized using Xilinx Vivado 2021.2 suite software and implemented on the Artix7 FPGA board, demonstrating that this design has the highest frequency achieving 239 MHz with an area of 75 LUTs, 50 FFs, and 28 Slices, respectively. The hardware efficiency metric is slightly higher than the K-RED design and significantly improved compared to other methods, at least $1.53\times$, $2.67\times$, and $2.74\times$, respectively. This design is suitable for both NTT and Point-Wise-Multiplication (PWM) modes.