Scheduling and Assignment in High Level Synthesis

Abstract

The continually increasing integration density and chip area will realize integrated circuits with more than a billion transistors in the next 10–20 years. Such complex integrated circuits enable the implementation of complete systems on one single chip. On the one hand this development leads to a growing specialisation and on the other hand to a continually stronger dominated share in design costs. The consequence of this development is the strengthened standardisation of chip structures in the form of standard cell circuits, gate arrays, sea-of-gates or the increasing importance of programmable gate arrays. On the other hand a stronger tendency towards design automation can be observed. In this connection the so-called “high level” synthesis is becoming more and more important. “High-level” synthesis describes the automation of the design above the logic level. While the usual tool support nowadays starts on the logic level, the “high-level” synthesis is understood as the (automatic) generation of a structure description on the register transfer level, resulting from an algorithmic description of behaviour. The advantages of this advanced design support are the low design costs and less design errors.