Unified System Construction (USC)

Abstract

When high-level synthesis research began, there were no VLSI chips. Design was assumed to be done with a fixed set of available modules [1]. In at least one case, these modules were assumed to be TTL chips [16]. Such chips and modules had a fixed cost, and wiring delays between chips were minimal compared to the processing delays on chip. Power consumption could easily be computed as the sum of the power consumptions of individual chips, and hot chips could be cooled with a heatsink. Partitioning onto multiple boards was performed manually, or at least handled separately from the high-level synthesis process. General-purpose multiprocessors were constructed only in research laboratories and special-purpose multiprocessors were expensive and constructed for only a few applications. Now, however, we are faced with a situation where high-level synthesis programs must design datapaths and controllers to fit on one or more VLSI chips and boards. For VLSI chips, a large portion of the chip area is consumed by wiring and wire delays can be significant. Partitioning must be performed to map problems onto multiple chips. There may be multiple processing elements, each with its own controller. Many problems are best implemented with multiprocessor architectures. Given this situation, high-level synthesis programs must take a number of factors into account that were by and large ignored in the early days of synthesis research.