Abstract
As demonstrated by the recent flurry of activity in this area, high-level synthesis [1] — often referred to as behavioral synthesis — is becoming an increasingly popular research topic. In this chapter, we present the most up-to-date description of the scheduling and allocation algorithms used in the HAL system [2-6], with emphasis on issues that, for lack of space, were not adequately covered in previous papers. These algorithms are not tied to the HAL synthesis methodology. Due to their flexibility, they can — and have been — integrated into more specialized high-level synthesis systems, as attested by their present use both in academia [20-26] and industry [27-29].
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References
M.C. McFarland, A.C. Parker, “Tutorial on High-Level Synthesis”, Proc. of the 25th Design Automation Conference, July 1988, pp. 330–336.
P.G. Paulin, J.P. Knight, E.F. Girczyc, “HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis”, Proc. of 23rd Design Automation Conference, July 1986, pp. 263–270.
P.G. Paulin, J.P. Knight, “Force-Directed Scheduling in Automatic Data Path Synthesis”, Proc. of the 24th Design Automation Conference, Miami Beach, July 1987, pp. 195–202.
P.G. Paulin, “High-Level Synthesis of Digital Circuits Using Global Scheduling and Binding Algorithms”, Ph.D. Thesis, Carleton University, Ottawa, Canada, February 1988.
P.G. Paulin, J.P. Knight, “Force-Directed Scheduling for the Behavioral Synthesis of ASICs”, IEEE Transactions on CAD of ICs and Systems, Vol. 8 (6), June 1989, pp. 661–679.
P.G. Paulin, J.P. Knight, “Algorithms for High-Level Synthesis”, IEEE Design & Test Magazine, Vol.6, No. 6, Dec. 1989, pp.18–31.
J.A. Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction”, IEEE Transactions on Computers C-30(7), July 1981, pp. 478–490.
R. Potasman et al, “Percolation Based Synthesis”, Proc. of the 27th Design Automation Conference, Orlando, FLA, June 1990, pp. 444–449.
„ “ Path-Based Scheduling for Synthesis”, IEEE Transactions on Computer-Aided Design, Vo1.10, No.1, January 1991, pp. 85–93.
N. Park, A.C. Parker, “SEHWA: A Program for Synthesis of Pipelines”, Proc. of the 23rd Design Automation Conference, Las Vegas, July 1986, pp. 454–460.
E.F. Girczyc, “Loop Winding -- a Data Flow Approach to Functional Pipelining”, Proc. of the International Symposium on Circuits and Systems (ISCAS), Philadelphia, May 1987, pp. 382–385.
F.D. Brewer, D.D. Gajski, “Knowledge-Based Control in Micro-Architecture Design”, Proceedings of the 24th Design Automation Conference, July 1987, pp. 203–209.
K.S. Hwang et al., “Constrained Conditional Resource Sharing in Pipeline Synthesis”, Proc. of the International Conf. on CAD, Nov. 1988, pp. 52–55.
M.C. McFarland, “Reevaluating the Design Space for Register-Transfer Hardware Synthesis”, Proc. of ICCAD, Nov. 1987, pp.262–265.
D.E. Thomas et al, “The System Architect’s Workbench”, Proceedings of the 25th Design Automation Conference, July 1988, pp. 337–343.
B.M. Pangrle, “Splicer: A Heuristic Approach to Connectivity Binding”, Proc. of the 25th Design Automation Conference, July 1988, pp. 536–541.
C.H. Gebotys, M.I. Elmasry, “VLSI Design Synthesis with Testability”, Proc. of 25th Design Automation Conference, July 1988, pp. 16–21.
C.H. Gebotys, M.I. Elmasry, “Workshop on High-Level Synthesis”, Chaired by E. Detjiens and Gaetano Borriello, Orcas Island, Washington, January 1988.
S.Y. Kung, H.J. Whitehouse, T. Kailath, “VLSI and Modern Signal Processing”, Prentice Hall, 1985, pp.258–264.
L. Stok, R. Van den Born, “EASY: Multiprocessor Architecture Optimisation”, Proc. of the International Workshop on Logic and Architecture Synthesis for Silicon Compilers, paper VII(3), Grenoble, France, May 1988.
P. Denyer (University of Edinburgh), Private Communication, Mar. 1989.
A.C. Parker, “Tutorial on High-Level Synthesis”, Presentation of the Canadian Conference on VLSI, Oct. 1990.
H. Kramer et al, “Data Path and Control Synthesis in the CADDY System”, Proc. of the International Workshop on Logic and Architecture Synthesis for Silicon Compilers, paper V(3), Grenoble, France, May 1988.
R. Cloutier, D.E. Thomas, “The Combination of Scheduling, Allocation and Mapping in a Single Algorithm”, Proc. of the 27th Design Automation Conference, June 1990, pp. 71–76.
C. Papachristou, H. Konuk, “A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm”, Proc. of the 27th Design Automation Conference, June 1990, pp. 77–83.
D. Dowling, K.E. Forward, “Scheduling Algorithms for the Translation of Behavioral Descriptions to Finite-State Machines”, Submitted to the European Conference on Design Automation, Feb. 1991.
J. Bhasker, M. Tong, “Exploring the Design Space in High-Level Synthesis”, Proc. of the IEEE Custom Integrated Circuits Conference, Oct. 1990, p. 29–2.1.
K.F. Pang, H.J. Huang, “Synthesis of Optimized ASIC DSP Systems”, Proc. of International Symposium on Circuits and Systems, Oct. 1990, pp. 2329–2332.
W.F.J. Verhaeg, J.H.M. Korst, P.E.R. Lippens, “Improved Force-Directed Scheduling”, Proc. of the European Conference on Design Automation, Amsterdam, Feb. 1991.
Tai,A.Ly, W.L. Elwood, E.F. Girczyc, “A Generalized Interconnect Model for Data Path Synthesis”, Proc. of the 27th DAC, June 1990, pp. 168–173.
A. Jerraya, P.G. Paulin, “SIF: A Synthesis Interchange Format for the Design and Synthesis of High-Level Controllers”, Proc. of the Fifth International Workshop on High-Level Synthesis, March 1991.
D. Harel et al, “Statecharts: A Working Environment for the Development of Complex Reactive Systems”, IEEE Trans. on Software Engineering, Vol. 16–4, Apr. 1990, pp.16–4.
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Paulin, P.G. (1991). Global Scheduling and Allocation Algorithms in the HAL System. In: Camposano, R., Wolf, W. (eds) High-Level VLSI Synthesis. The Springer International Series in Engineering and Computer Science, vol 136. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3966-7_11
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DOI: https://doi.org/10.1007/978-1-4615-3966-7_11
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