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Memory Architectures

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Handbook of Hardware/Software Codesign

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Abstract

In this chapter we discuss the topic of memory organization in embedded systems and Systems-on-Chips (SoCs). We start with the simplest hardware-based systems needing registers for storage and proceed to hardware/software codesigned systems with several standard structures such as Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM). In the process, we touch upon concepts such as caches and Scratchpad Memories (SPMs) . In general, the emphasis is on concepts that are more generally found in SoCs and less on general-purpose computing systems, although this distinction is not very clearly defined with respect to the memory subsystem. We touch upon implementations of these ideas in modern research and commercial scenarios. In this chapter, we also point out issues arising in the context of the memory architectures that become exported as problems to be addressed by the compiler and system designer.

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Acknowledgements

The author acknowledges Lokesh Siddhu for generating the data for memory configurations reported in Figs. 23 and 24.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, 110016, New Delhi, India

    Preeti Ranjan Panda

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  1. Preeti Ranjan Panda
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Correspondence to Preeti Ranjan Panda .

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Editors and Affiliations

  1. Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Friedrich-Alexander-Universität , Nürnberg, Germany

    Jürgen Teich

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Panda, P. (2016). Memory Architectures. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7358-4_14-1

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  • DOI: https://doi.org/10.1007/978-94-017-7358-4_14-1

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  • Print ISBN: 978-94-017-7358-4

  • Online ISBN: 978-94-017-7358-4

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