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Reconfigurable Architectures

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Abstract

Reconfigurable architecture is a computer architecture combining some of the flexibility of software with the high performance of hardware. It has configurable fabric that performs a specific data-dominated task, such as image processing or pattern matching, quickly as a dedicated piece of hardware. Once the task has been executed, the hardware can be adjusted to do some other task. This allows the reconfigurable architecture to provide the flexibility of software with the speed of hardware. This chapter discusses two major streams of reconfigurable architecture : Field-Programmable Gate Array (FPGA) and Coarse Grained Reconfigurable Architecture (CGRA) . It gives a brief explanation of the merits and usage of reconfigurable architecture and explains basic FPGA and CGRA architectures. It also explains techniques for mapping applications onto FPGAs and CGRAs .

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References

  1. Ahn M, Yoon J, Paek Y, Kim Y, Kiemb M, Choi K (2006) A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In: Proceedings of the design, automation and test in Europe, DATE ’06, vol 1, p 6

    Google Scholar 

  2. Altera arria 10 FPGA. www.altera.com. Accessed 28 Nov 2015

  3. Aletà A, Codina JM, Sánchez J, González A (2001) Graph-partitioning based instruction scheduling for clustered processors. In: Proceedings of the 34th annual ACM/IEEE international symposium on microarchitecture, MICRO 34. IEEE Computer Society, Washington, DC, pp 150–159

    Chapter  Google Scholar 

  4. Altera stratix v FPGA. www.altera.com. Accessed 28 Nov 2015

  5. Ansaloni G, Bonzini P, Pozzi L (2011) EGRA: a coarse grained reconfigurable architectural template. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(6):1062–1074

    Article  Google Scholar 

  6. Baar T, Brucker P, Knust S (1999) Tabu search algorithms and lower bounds for the resource-constrained project scheduling problem. In: Voss S, Martello S, Osman I, Roucairol C (eds) Meta-heuristics. Springer US, pp 1–18. doi: 10.1007/978-1-4615-5775-3_1

    Google Scholar 

  7. Bean JC (1994) Genetic algorithms and random keys for sequencing and optimization. ORSA J Comput 6(2):154–160. doi: 10.1287/ijoc.6.2.154, http://dx.doi.org/10.1287/ijoc.6.2.154

    Google Scholar 

  8. Becker J, Glesner M (2000) Fast communication mechanisms in coarse-grained dynamically reconfigurable array architecture. In: The 2000 international conference on parallel and distributed processing techniques and applications (PDPTA’2000), Las Vegas

    Google Scholar 

  9. Betz V, Rose J (1997) VPR: a new packing, placement and routing tool for FPGA research. In: Proceedings of the 7th international workshop on field-programmable logic and applications, FPL ’97. Springer, London, pp 213–222

    Chapter  Google Scholar 

  10. Bouleimen K, Lecocq H (2003) A new efficient simulated annealing algorithm for the resource-constrained project scheduling problem and its multiple mode version. Eur J Oper Res 149(2):268–281. doi: 10.1016/S0377-2217(02)00761-0. Sequencing and Scheduling

    Google Scholar 

  11. Canis A, Choi J, Aldham M, Zhang V, Kammoona A, Anderson JH, Brown S, Czajkowski T (2011) LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In: Proceedings of the 19th ACM/SIGDA international symposium on field programmable gate arrays, FPGA ’11. ACM, New York, pp 33–36. doi: 10.1145/1950413.1950423

    Chapter  Google Scholar 

  12. Chattopadhyay A (2013) Ingredients of adaptability: a survey of reconfigurable processors. VLSI Des 2013:10:10–10:10

    Google Scholar 

  13. Che S, Li J, Sheaffer J, Skadron K, Lach J (2008) Accelerating compute-intensive applications with GPUs and FPGAs. In: Proceedings of the symposium on application specific processors, SASP 2008, pp 101–107

    Google Scholar 

  14. Chen D, Cong J (2004) Register binding and port assignment for multiplexer optimization. In: Proceedings of the 2004 Asia and South Pacific design automation conference, ASP-DAC ’04. IEEE Press, Piscataway, pp 68–73

    Google Scholar 

  15. Chen L, Mitra T (2014) Graph minor approach for application mapping on CGRAs. ACM Trans Reconfig Technol Syst 7(3):21:1–21:25

    Google Scholar 

  16. Chen KC, Cong J, Ding Y, Kahng A, Trajmar P (1992) Dag-map: graph-based FPGA technology mapping for delay optimization. IEEE Des Test Comput 9(3):7–20. doi: 10.1109/54.156154

    Article  Google Scholar 

  17. Chen D, Cong J, Fan Y, Han G, Jiang W, Zhang Z (2005) xPilot: a platform-based behavioral synthesis system. SRC TechCon 5

    Google Scholar 

  18. Chen D, Cong J, Fan Y, Wan L (2010) LOPASS: a low-power architectural synthesis system for FPGAs With interconnect estimation and optimization. IEEE Trans VLSI Syst 18(4):564–577

    Article  Google Scholar 

  19. Cho JH, Kim YD (1997) A simulated annealing algorithm for resource constrained project scheduling problems. J Oper Res Soc 48(7):736–744

    Article  MATH  Google Scholar 

  20. Choi K (2011) Coarse-grained reconfigurable array: architecture and application mapping. IPSJ Trans SystLSI Des Methodol 4:31–46. doi: 10.2197/ipsjtsldm.4.31

    Article  Google Scholar 

  21. Cong J, Minkovich K (2010) Lut-based FPGA technology mapping for reliability. In: Proceedings of the 47th design automation conference, DAC ’10. ACM, New York, pp 517–522. doi: 10.1145/1837274.1837401

    Chapter  Google Scholar 

  22. Cong J, Wu C, Ding Y (1999) Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on field programmable gate arrays, FPGA ’99. ACM, New York, pp 29–35. doi: 10.1145/296399.296425

    Chapter  Google Scholar 

  23. Coussy P, Gajski D, Meredith M, Takach A: An introduction to high-level synthesis. IEEE Des Test Comput 26(4):8–17 (2009). doi: 10.1109/MDT.2009.69

    Article  Google Scholar 

  24. Coussy P, Lhairech-Lebreton G, Heller D, Martin E (2010) Gaut–a free and open source high-level synthesis tool. In: IEEE DATE

    Google Scholar 

  25. De Sutter B, Raghavan P, Lambrechts A (2010) Coarse-grained reconfigurable array architectures. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of signal processing systems. Springer, Boston, pp 449–484. doi: 10.1007/978-1-4419-6345-1_17

    Chapter  Google Scholar 

  26. Dimitroulakos G, Galanis MD, Goutis CE (2005) Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays. In: 2005 IEEE international conference on application-specific systems, architecture processors (ASAP’05), pp 161–168. doi: 10.1109/ASAP.2005.12

    Google Scholar 

  27. Dimitroulakos G, Georgiopoulos S, Galanis MD, Goutis CE (2009) Resource aware mapping on coarse grained reconfigurable arrays. Microprocess Microsyst 33(2):91–105

    Article  Google Scholar 

  28. Dirk K (2012) Partial reconfiguration on FPGAs: architectures, tools and applications. Springer, New York

    Google Scholar 

  29. Dynamic reconfiguration in Stratix IV devices (2014). Accessed 27 Nov 2015

    Google Scholar 

  30. Ebeling C, Cronquist D, Franklin P (1996) Rapid – reconfigurable pipelined datapath. In: Hartenstein R, Glesner M (eds) Field-programmable logic smart applications, new paradigms and compilers. Lecture notes in computer science, vol 1142. Springer, Berlin/Heidelberg, pp 126–135

    Chapter  Google Scholar 

  31. Friedman S, Carroll A, Van Essen B, Ylvisaker B, Ebeling C, Hauck S (2009) SPR: an architecture-adaptive cgra mapping tool. In: Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, FPGA ’09. ACM, New York, pp 191–200. doi: 10.1145/1508128.1508158

    Chapter  Google Scholar 

  32. Galanis M, Dimitroulakos G, Goutis C (2006) Mapping DSP applications on processor/coarse-grain reconfigurable array architectures. In: Proceedings 2006 IEEE international symposium on circuits and systems, ISCAS 2006, p. 4

    Google Scholar 

  33. Garfinkel RS, Nemhauser GL (1972) Integer programming, vol 4. Wiley, New York

    MATH  Google Scholar 

  34. Goldstein S, Schmit H, Budiu M, Cadambi S, Moe M, Taylor R (2000) Piperench: a reconfigurable architecture and compiler. Computer 33(4):70–77

    Article  Google Scholar 

  35. Hamzeh M, Shrivastava A, Vrudhula S (2012) EPIMap: using epimorphism to map applications on CGRAs. In: Proceedings of the 49th annual design automation conference, DAC ’12. ACM, New York, pp 1284–1291

    Chapter  Google Scholar 

  36. Hamzeh M, Shrivastava A, Vrudhula S (2013) REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). In: 2013 50th ACM/EDAC/IEEE design automation conference (DAC), pp 1–10. doi: 10.1145/2463209.2488756

    Google Scholar 

  37. Han KH, Kim JH (2004) Quantum-inspired evolutionary algorithms with a new termination criterion, H/sub/spl epsi//gate, and two-phase scheme. IEEE Trans Evol Comput 8(2):156–169. doi: 10.1109/TEVC.2004.823467

    Article  MathSciNet  Google Scholar 

  38. Han K, Ahn J, Choi K (2013) Power-efficient predication techniques for acceleration of control flow execution on CGRA. ACM Trans Archit Code Optim 10(2):8:1–8:25. doi: 10.1145/2459316.2459319

    Google Scholar 

  39. Hartenstein R (2001) A decade of reconfigurable computing: a visionary retrospective. In: Proceedings of the design, automation and test in Europe, Conference and Exhibition 2001, pp 642–649

    Google Scholar 

  40. Hatanaka A, Bagherzadeh N (2007) A modulo scheduling algorithm for a coarse-grain reconfigurable array template. In: IEEE international parallel and distributed processing symposium, IPDPS 2007, pp 1–8

    Google Scholar 

  41. Hauck S, Fry T, Hosler M, Kao J (2004) The chimaera reconfigurable functional unit. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(2):206–217

    Article  Google Scholar 

  42. Hauser J, Wawrzynek J (1997) Garp: a mips processor with a reconfigurable coprocessor. In: Proceedings of the 5th annual IEEE symposium on field-programmable custom computing machines, 1997, pp 12–21

    Google Scholar 

  43. Hwang CT, Lee JH, Hsu YC (1991) A formal approach to the scheduling problem in high level synthesis. IEEE Trans Comput-Aided Des Integr Circuits Syst 10(4):464–475. doi: 10.1109/43.75629

    Article  Google Scholar 

  44. Jo M, Lee D, Han K, Choi K (2014) Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. Integr {VLSI} J 47(2):232–241. doi: 10.1016/j.vlsi.2013.08.003

    Article  Google Scholar 

  45. Kernighan BW, Lin S (1970) An efficient heuristic procedure for partitioning graphs. Bell Syst Tech J 49:291–307

    Article  MATH  Google Scholar 

  46. Kestur S, Davis J, Williams O (2010) Blas comparison on FPGA, CPU and GPU. In: 2010 IEEE computer society annual symposium on VLSI (ISVLSI), pp 288–293. doi: 10.1109/ISVLSI.2010.84

    Google Scholar 

  47. Kim Y, Kiemb M, Park C, Jung J, Choi K (2005) Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization. In: Design, automation and test in Europe, vol 1 pp 12–17. doi: 10.1109/DATE.2005.260

    Google Scholar 

  48. Kim Y, Mahapatra RN, Park I, Choi K (2009) Low power reconfiguration technique for coarse-grained reconfigurable architecture. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(5):593–603. doi: 10.1109/TVLSI.2008.2006039

    Article  Google Scholar 

  49. Kim Y, Lee J, Shrivastava A, Paek Y (2011) Memory access optimization in compilation for coarse-grained reconfigurable architectures. ACM Trans Des Autom Electron Syst 16(4):42:1–42:27. doi: 10.1145/2003695.2003702

    Google Scholar 

  50. Kim Y, Lee J, Shrivastava A, Yoon J, Cho D, Paek Y (2011) High throughput data mapping for coarse-grained reconfigurable architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(11):1599–1609

    Article  Google Scholar 

  51. Kim C, Chung M, Cho Y, Konijnenburg M, Ryu S, Kim J (2012) ULP-SRP: Ultra low power samsung reconfigurable processor for biomedical applications. In: 2012 international conference on field-programmable technology (FPT), pp 329–334. doi: 10.1109/FPT.2012.6412157

    Google Scholar 

  52. Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science 220(4598):671–680. doi: 10.1126/science.220.4598.671

    Article  MathSciNet  MATH  Google Scholar 

  53. Koch D, Beckhoff C, Teich J (2009) Minimizing internal fragmentation by fine-grained two-dimensional module placement for runtime reconfigurable systems. In: 17th annual IEEE symposium on field-programmable custom computing machines (FCCM 2009). IEEE Computer Society, pp 251–254

    Google Scholar 

  54. Koch D, Beckhoff C, Tørrison J (2010) Advanced partial run-time reconfiguration on spartan-6 fpgas. In: 2010 international conference on field-programmable technology (FPT), pp 361–364

    Google Scholar 

  55. Koch D, Beckhoff C, Wold A, Torresen J (2013) Easypr – an easy usable open-source PR system. In: 2013 international conference on field-programmable technology (FPT), pp 414–417

    Google Scholar 

  56. Kurdahi F, Parker A (1987) Real: a program for register allocation. In: 24th conference on design automation, pp 210–215. doi: 10.1109/DAC.1987.203245

    Google Scholar 

  57. Langhammer M, Pasca B (2015) Floating-point DSP block architecture for FPGAs. In: Proceedings of the 2015 ACM/SIGDA international symposium on field-programmable gate arrays, FPGA ’15. ACM, New York, pp 117–125. doi: 10.1145/2684746.2689071

    Google Scholar 

  58. Lanuzza M, Perri S, Corsonello P, Margala M (2007) A new reconfigurable coarse-grain architecture for multimedia applications. In: 2007 second NASA/ESA conference on adaptive hardware and systems, AHS 2007, pp 119–126

    Google Scholar 

  59. Lattner C (2002) LLVM: an infrastructure for multi-stage optimization. Master’s thesis, Computer Science Department, University of Illinois at Urbana-Champaign, Urbana. http://llvm.org/pubs/2002-12-LattnerMSThesis.pdf

  60. Lee Je, Choi K, Dutt ND (2003) An algorithm for mapping loops onto coarse-grained reconfigurable architectures. SIGPLAN Not 38(7):183–188

    Article  Google Scholar 

  61. Lee G, Lee S, Choi K (2008) Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques. In: Proceedings of the international SoC design conference, ISOCC ’08, vol 01, pp I–395–I–398

    Google Scholar 

  62. Lee D, Jo M, Han K, Choi K (2009) Flora: coarse-grained reconfigurable architecture with floating-point operation capability. In: 2009 international conference on field-programmable technology, FPT 2009, pp 376–379

    Google Scholar 

  63. Lee G, Choi K, Dutt N (2011) Mapping multi-domain applications onto coarse-grained reconfigurable architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(5):637–650

    Article  Google Scholar 

  64. Lee H, Nguyen D, Lee J (2015) Optimizing stream program performance on cgra-based systems. In: Proceedings of the 52nd annual design automation conference, DAC ’15. ACM, New York, pp 110:1–110:6

    Google Scholar 

  65. Leijten J, Burns G, Huisken J, Waterlander E, van Wel A (2003) AVISPA: a massively parallel reconfigurable accelerator. In: Proceedings of the 2003 international symposium on system-on-chip, pp 165–168

    Google Scholar 

  66. Li S, Ebeling C (2004) Quickroute: a fast routing algorithm for pipelined architectures. In: Proceedings of the 2004 IEEE international conference on field-programmable technology, pp 73–80. doi: 10.1109/FPT.2004.1393253

    Google Scholar 

  67. Liang C, Huang X (2008) Smartcell: a power-efficient reconfigurable architecture for data streaming applications. In: 2008 IEEE workshop on signal processing systems, SiPS 2008, pp 257–262

    Google Scholar 

  68. Lie W, Feng-yan W: Dynamic partial reconfiguration in FPGAs. In: 2009 third international symposium on intelligent information technology application, IITA 2009, vol 2, pp 445–448 (2009)

    Google Scholar 

  69. Lysaght P, Blodget B, Mason J, Young J, Bridgford B (2006) Invited paper: enhanced architectures, design methodologies and cad tools for dynamic reconfiguration of Xilinx FPGAs. In: FPL, pp 1–6. IEEE

    Google Scholar 

  70. Marshall A, Stansfield T, Kostarnov I, Vuillemin J, Hutchings B (1999) A reconfigurable arithmetic array for multimedia applications. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on field programmable gate arrays, FPGA ’99. ACM, New York, pp 135–143

    Chapter  Google Scholar 

  71. McMurchie L, Ebeling C (1995) Pathfinder: a negotiation-based performance-driven router for FPGAs. In: Proceedings of the third international ACM symposium on field-programmable gate arrays, FPGA ’95, pp 111–117. doi: 10.1109/FPGA.1995.242049

    Google Scholar 

  72. Mehta N (2015) Ultrascale architecture: highest device utilization, performance, and scalability, WP455 (v1.2), October 29, 2015

    Google Scholar 

  73. Mei B, Vernalde S, Verkest D, De Man H, Lauwereins R (2003) Adres: an architecture with tightly coupled vliw processor and coarse-grained reconfigurable matrix. In: Cheung PYK, Constantinides G (eds) Field programmable logic and application. Lecture notes in computer science, vol 2778. Springer, Berlin/Heidelberg, pp 61–70

    Chapter  Google Scholar 

  74. Mei B, Vernalde S, Verkest D, De Man H, Lauwereins R (2003) Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. In: Proceedings of the conference on design, automation and test in Europe – DATE ’03, vol 1. IEEE Computer Society, Washington, DC, p 10296

    Google Scholar 

  75. Mei B, Vernalde S, Verkest D, Lauwereins R (2004) Design methodology for a tightly coupled vliw/reconfigurable matrix architecture: a case study. In: Proceedings of the 2004 design, automation and test in Europe conference and exhibition, vol 2, pp 1224–1229

    Google Scholar 

  76. Mei B, Lambrechts A, Mignolet JY, Verkest D, Lauwereins R (2005) Architecture exploration for a reconfigurable architecture template. IEEE Des Test Comput 22(2):90–101

    Article  Google Scholar 

  77. MicroBlaze processor: MicroBlaze soft processor core (2012). http://www.xilinx.com/products/design-tools/microblaze.html

  78. Mirsky E, DeHon A (1996) Matrix: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In: Proceedings of the IEEE symposium on FPGAs for custom computing machines, pp 157–166

    Google Scholar 

  79. Miyamori T, Olukotun K (1998) Remarc: reconfigurable multimedia array coprocessor. In: IEICE transactions on information and systems E82-D, pp 389–397

    Google Scholar 

  80. Moghaddam MS, Paul K, Balakrishnan M (2013) Design and implementation of high performance architectures with partially reconfigurable cgras. In: 2013 IEEE 27th international parallel and distributed processing symposium workshops PhD forum (IPDPSW), pp 202–211. doi: 10.1109/IPDPSW.2013.121

    Google Scholar 

  81. Moghaddam MS, Paul K, Balakrishnan M (2014) Mapping tasks to a dynamically reconfigurable coarse grained array. In: 2014 IEEE 22nd annual international symposium on field-programmable custom computing machines (FCCM), pp 33–33. doi: 10.1109/FCCM.2014.20

    Google Scholar 

  82. Moghaddam M, Balakrishnan M, Paul K (2015) Partial reconfiguration for dynamic mapping of task graphs onto 2d mesh platform. In: Sano K, Soudris D, Hübner M, Diniz PC (eds) Applied reconfigurable computing. Lecture notes in computer science, vol 9040. Springer, pp 373–382

    Google Scholar 

  83. Moon J, Moser L (1965) On cliques in graphs. Isr J Math 3(1):23–28. doi: 10.1007/BF02760024

    Article  MathSciNet  MATH  Google Scholar 

  84. MultiTrack interconnect in Stratix III devices (2009)

    Google Scholar 

  85. Oh T, Egger B, Park H, Mahlke S (2009) Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. SIGPLAN Not 44(7):21–30

    Article  Google Scholar 

  86. Park S, Choi K (2011) An approach to code compression for CGRA. In: 2011 3rd Asia symposium on quality electronic design (ASQED), pp 240–245. doi: 10.1109/ASQED.2011.6111753

    Google Scholar 

  87. Park IC, Kyung CM (1991) Fast and near optimal scheduling in automatic data path synthesis. In: 28th ACM/IEEE design automation conference, pp 680–685

    Google Scholar 

  88. Park H, Fan K, Kudlur M, Mahlke S (2006) Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. In: Proceedings of the 2006 international conference on compilers, architecture and synthesis for embedded systems, CASES ’06. ACM, New York, pp 136–146

    Chapter  Google Scholar 

  89. Park H, Fan K, Mahlke SA, Oh T, Kim H, Kim HS (2008) Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: Proceedings of the 17th international conference on parallel architectures and compilation techniques, PACT ’08. ACM, New York, pp 166–176

    Chapter  Google Scholar 

  90. Park JJK, Park Y, Mahlke S (2013) Efficient execution of augmented reality applications on mobile programmable accelerators. In: 2013 international conference on field-programmable technology (FPT), pp 176–183. doi: 10.1109/FPT.2013.6718350

    Google Scholar 

  91. Patel K, Bleakley CJ (2010) Systolic algorithm mapping for coarse grained reconfigurable array architectures. In: Proceedings of the 6th international conference on reconfigurable computing: architectures, tools and applications, ARC’10, pp 351–357. Springer, Berlin/Heidelberg

    Chapter  Google Scholar 

  92. Patel K, McGettrick S, Bleakley CJ (2011) Syscore: a coarse grained reconfigurable array architecture for low energy biosignal processing. In: 2011 IEEE 19th annual international symposium on field-programmable custom computing machines (FCCM), pp 109–112

    Google Scholar 

  93. Paul K, Dash C, Moghaddam M (2012) reMORPH: a runtime reconfigurable architecture. In: 2012 15th Euromicro conference on digital system design (DSD), pp 26–33

    Google Scholar 

  94. Pinson E, Prins C, Rullier F (1994) Using tabu search for solving the resource-constrained project scheduling problem. In: Proceedings of the 4th international workshop on project management and scheduling, Leuven, pp 102–106

    Google Scholar 

  95. Rau BR (1994) Iterative modulo scheduling: an algorithm for software pipelining loops. In: Proceedings of the 27th annual international symposium on microarchitecture, MICRO 27. ACM, New York, pp 63–74. doi: 10.1145/192724.192731

    Chapter  Google Scholar 

  96. Salefski B, Caglar L (2001) Re-configurable computing in wireless. In: Proceedings of 2001 design automation conference, pp 178–183

    Google Scholar 

  97. Sanchez E, Sterpone L, Ullah A (2014) Effective emulation of permanent faults in asics through dynamically reconfigurable FPGAs. In: 2014 24th international conference on field programmable logic and applications (FPL), pp 1–6

    Google Scholar 

  98. Sato T, Watanabe H, Shiba K (2005) Implementation of dynamically reconfigurable processor dapdna-2. In: 2005 IEEE VLSI-TSA international symposium on VLSI design, automation and test (VLSI-TSA-DAT), pp 323–324

    Google Scholar 

  99. Sato T, Watanabe H, Shiba K: Implementation of dynamically reconfigurable processor dapdna-2. In: 2005 IEEE VLSI-TSA international symposium on VLSI design, automation and test (VLSI-TSA-DAT), pp 323–324 (2005)

    Google Scholar 

  100. Singh H, Lee MH, Lu G, Kurdahi F, Bagherzadeh N, Chaves Filho E (2000) Morphosys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans Comput 49(5):465–481

    Article  Google Scholar 

  101. Smit GJM, Kokkeler ABJ, Wolkotte PT, Hölzenspies PKF, van de Burgwal MD, Heysters PM (2007) The chameleon architecture for streaming DSP applications. EURASIP J Embed Syst 2007(1):1–10

    Article  Google Scholar 

  102. SYSTEMS T (2016) Coarse-grained reconfigurable architecture. http://www.trentonsystems.com/blog/intel-cpu-computing/moores-law-pushing-processor-technology-to-14-nanometers/

  103. Tehre V, Kshirsagar R (2012) Survey on coarse grained reconfigurable architectures. Int J Comput Appl 48(16):1–7. Full text available

    Google Scholar 

  104. Todman T, Constantinides G, Wilton S, Mencer O, Luk W, Cheung P (2005) Reconfigurable computing: architectures and design methods. IEE Proc Comput Digital Tech 152(2):193–207

    Article  Google Scholar 

  105. Trimberger S (2015) Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc IEEE 103(3):318–331

    Article  Google Scholar 

  106. Tsu W, Macy K, Joshi A, Huang R, Walker N, Tung T, Rowhani O, George V, Wawrzynek J, DeHon A (1999) HSRA: high-speed, hierarchical synchronous reconfigurable array. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on field programmable gate arrays, FPGA ’99. ACM, New York, pp 125–134

    Chapter  Google Scholar 

  107. University S (2016) SUIF compiler system. http://suif.stanford.edu/

  108. Villarreal J, Park A, Najjar W, Halstead R (2010) Designing modular hardware accelerators in C with ROCCC 2.0. In: 2010 18th IEEE annual international symposium on field-programmable custom computing machines (FCCM), pp 127–134. doi: 10.1109/FCCM.2010.28

    Google Scholar 

  109. Vivado HLS: Xilinx Vivado Design Suite, Inc. (2012). http://www.xilinx.com/products/design-tools/vivado.html

    Google Scholar 

  110. Waingold E, Taylor M, Srikrishna D, Sarkar V, Lee W, Lee V, Kim J, Frank M, Finch P, Barua R, Babb J, Amarasinghe S, Agarwal A (1997) Baring it all to software: raw machines. Computer 30(9):86–93

    Article  Google Scholar 

  111. Watkins MA, Albonesi DH (2010) ReMAP: a reconfigurable heterogeneous multicore architecture. In: Proceedings of the 2010 43rd annual IEEE/ACM international symposium on microarchitecture, MICRO ’43. IEEE Computer Society, Washington, DC, pp 497–508

    Chapter  Google Scholar 

  112. Xcell Journal Issue 52:. http://www.xilinx.com/publications/archives/xcell/Xcell52.pdf

  113. Xilinx 7 series FPGA. www.xilinx.com. Accessed 27 Nov 2015

  114. Xilinx (2012) Virtex 5 FPGA user guide

    Google Scholar 

  115. Xilinx (2014) 7 series FPGAs configurable logic block

    Google Scholar 

  116. Yoon JW, Shrivastava A, Park S, Ahn M, Jeyapaul R, Paek Y (2008) SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. In: 2008 Asia and South Pacific design automation conference, pp 776–782. doi: 10.1109/ASPDAC.2008.4484056

    Google Scholar 

  117. Yoon J, Shrivastava A, Park S, Ahn M, Paek Y (2009) A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(11):1565–1578

    Article  Google Scholar 

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Mansureh, M.S., Cho, JM., Choi, K. (2016). Reconfigurable Architectures. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7358-4_12-1

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  • DOI: https://doi.org/10.1007/978-94-017-7358-4_12-1

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-017-7358-4

  • Online ISBN: 978-94-017-7358-4

  • eBook Packages: Springer Reference EngineeringReference Module Computer Science and Engineering

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