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On the Node Complexity of Threshold Gate Circuits with Sub-linear Fan-ins

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Neural Networks and Soft Computing

Part of the book series: Advances in Soft Computing ((AINSC,volume 19))

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Abstract

This paper discusses size-optimal solutions for implementing arbitrary Boolean functions using threshold gates. After presenting the state-of-the-art, we start from the result of Horne and Hush [12], which shows that threshold gate circuits restricted to fan-in 2 can implement arbitrary Boolean functions, but require O(2n/n) gates in 2n layers. This result will be generalized to arbitrary fan-ins (Δ), lowering the depth to n/logΔ + n/Δ, and proving that all the (relative) minimums of size are obtained for sub-linear fan-ins (Δ < n − logn). The fact that size-optimal solutions have sub-linear fan-ins is encouraging, as the area and the delay of VLSI implementations are related to the fan-in of the gates.

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Author information

Authors and Affiliations

  1. School of Electrical Engineering & Computer Science, Washington State University, 102 Spokane Str. (EME), PO Box 642752, Pullman, WA, 99164-2752, USA

    Valeriu Beiu

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  1. Valeriu Beiu
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Editors and Affiliations

  1. Department of Computer Engineering, Technical University Częstochowa, Al. Armii Krajowej 36, 42-200, Częstochowa, Poland

    Leszek Rutkowski

  2. Systems Research Institute, Polish Academy of Sciences, ul. Newelska 6, 01-447, Warsaw, Poland

    Janusz Kacprzyk

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© 2003 Springer-Verlag Berlin Heidelberg

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Beiu, V. (2003). On the Node Complexity of Threshold Gate Circuits with Sub-linear Fan-ins. In: Rutkowski, L., Kacprzyk, J. (eds) Neural Networks and Soft Computing. Advances in Soft Computing, vol 19. Physica, Heidelberg. https://doi.org/10.1007/978-3-7908-1902-1_18

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  • DOI: https://doi.org/10.1007/978-3-7908-1902-1_18

  • Publisher Name: Physica, Heidelberg

  • Print ISBN: 978-3-7908-0005-0

  • Online ISBN: 978-3-7908-1902-1

  • eBook Packages: Springer Book Archive

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