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References
R.C. Eden, B.M. Welch: “Ultra High Speed GaAs VLSI: Approaches, Potential and Progress,” in VLSI Electronics: Micro structure Science, Volume 3, ed. by N. Einspruch (Academic, New York 1981)
H. Kroemer: Heterostructure bipolar transistors and integrated circuits. IEEE Proc. 70, No.1 (1982), and other papers in this special issue on Very Fast Solid State Technology
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T.J. Maloney: “AIGaAs Heterojunction Gate GaAs FETs by Organometallic and Molecular Beam Epitaxy,” 39th Annual Device Research Conference, Santa Barbara, June 1981, Paper VA-8
T. Mimura, S. Hiyamizu, T. Fujii, K. Nanbu: “A New Field-Effect Transistor with Selectively Doped GaAs/N-AlxGa-[-xAs Heterojunctions,” Jpn. J. Appl. Phys. Lett. 19, 225–227 (1980)
T. Minura, S. Hiyamizu, H. Idhikawa, T. Misugi: “An Enhancement-Mode High Electron Mobility Transistor for VLSI,” High Speed Digital Technologies Conf., Paper III-5, San Diego, Jan. 14, 1981
R.J. Malik, M.A. Hoilis, L.F. Eastman, D.W. Woodard, C.E.C. Wood, T.R. Aucoin: “GaAs Planar Doped-Barrier Transistors,” 39th Annual Device Research Conference, Santa Barbara, June 1981, Paper VA-7
T. Mizutani: “Gigabit Logic Operation with Enhancement-Mode GaAs MESFET IC’s,” IEEE MTT-S Workshop on Gigabit Logic for Microwave Systems, May 1980. Data presented for Lg = 0.6 ym 15-stage inverter ring oscillators with room temperature speeds up to τd = 30 ps at PD =1.9 mW/gate or τd = 63 ps at PD = 100 yW/gate, and 77K speeds up to τd = 17.5 ps at PD = 9.2 mW/gate. Earlier, Lg = 0.8-µm data were presented in: T. Mizutani, N. Kato, M. Ida, M. Ohmori: High-speed enhancement-mode GaAs MESFET logic. IEEE Trans. MTT-28, 479–483 (1980)
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© 1982 Springer-Verlag Berlin Heidelberg
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Barbe, D.F. (1982). Erratum to: GaAs Digital Integrated Circuits for Ultra High Speed LSI/VLSI. In: Barbe, D.F. (eds) Very Large Scale Integration (VLSI). Springer Series in Electrophysics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-88640-9_11
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