Abstract
A general trend in computers today is to increase the complexity of architectures commensurate with the increasing potential of implementation technologies. Consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation[7]. The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend. Our initial design is called RISC I.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Frank, E.H. and Sproull, R.F., “An Approach to Debugging Custom Integrated Circuits,” Carnegie-Mellon Computer Science Research Review 1979-80, pp. 21–36 (July, 1981).
Joy, W.N., Fabry, R.S., and Sklower, K., Seventh Edition, Virtual VAX-11 Vernon, Computer Science Division, Dept of EECS, U. C. Berkeley June, 1981.
Lattin, V.V., Bayliss, J.A., Budde, D.L, Colley, S.R., Cox, G.V., Goodman, A.L., Rattner, J.R., Richardson, W.S., and Swanson, R.C., “A 32b VLSI Micromainframe Computer System,” Proc. IEEE International Solid-State Circuits Conference, pp. 110–111 (February, 1981 ).
Lattin, W.W., Bayliss, J.A., Budde, D.L., Rattner, J.R., and Richardson, W.S., “A Methodology for VLSI Chip Design,” Lambda, pp. 34–44 (Second Quarter, 1981 ).
Newton, A.R., Pederson, D.O., Sangiovanni-Vincentelli, A.L., and Sequin, C.H., “Design Aids for VLSI: The Berkeley Perspective,” IEEE Transactions on Circuits and Systems, (July 1961).
Ousterhout, J., “Caesar: An Interactive Editor for VLSI Circuits,” VLSI Design II(4)(Fourth Quarter, 1981). to appear
Patterson, D.A. and Ditzel, D.R., “The Case for the Reduced Instruction Set Computer,” Computer Architecture News 8(6) pp. 25–33 (15 October 1980 ).
Patterson, D.A. and Sequin, C.H., “Design Considerations for Single-Chip Computers of the Future,” IEEE Transactions on Computers C-29(2) pp. 108–116 ( February 1980 ). Joint Special Issue on Microprocessors and Microcomputers.
Patterson, D.A. and Sequin, C.H., “RISC I: A Reduced Instruction Set VLSI Computer,” Proc. Eighth International Symposium on Computer Architecture, pp. 443–457, (May 1981).
Rattner, J.R.,Private Communication, August 1981
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1981 Carnegie-Mellon University
About this chapter
Cite this chapter
Fitzpatrick, D.T. et al. (1981). VLSI Implementations of a Reduced Instruction Set Computer. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_36
Download citation
DOI: https://doi.org/10.1007/978-3-642-68402-9_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-68404-3
Online ISBN: 978-3-642-68402-9
eBook Packages: Springer Book Archive