Skip to main content
SpringerLink
Log in

Testing Embedded Memories: A Survey

  • Conference paper
Mathematical and Engineering Methods in Computer Science (MEMICS 2012)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 7721))

Abstract

According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chips (SoCs) content in the future, approaching 90% in in some cases. Therefore, the memory yield and quality will have a dramatic impact on the overall SoC cost and outgoing product quality. Meeting a high memory yield and quality requires understanding memory designs, modeling their faulty behaviors in appropriate and accurate way, designing adequate tests and diagnosis strategies as well as efficient Design-for-Testability and Built-In-Self-Test (BIST) schemes. This paper presents the state of art in memory testing including fault modeling, test design and BIST. Further research challenges and opportunities are discussed in enabling testing (embedded) memories in the nano-era.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Marinissen, E.J., et al.: Challenges in Embedded Memory Design and Test. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (2005)

    Google Scholar 

  2. Inoue, M., et al.: A New Test Evaluation Chip for Lower Cost Memory Tests. IEEE Design and Test of Computers 10(1), 15–19 (1993)

    Article  Google Scholar 

  3. Mookerjee, R.: Segmentation: A Technique for Adapting High-Performance Logic ATE to Test High-Density, High-Speed SRAMs. In: IEEE Workshop on Memory Test, pp. 120–124 (1993)

    Google Scholar 

  4. Suk, D.S., Reddy, S.M.: A March Test for Functional Faults in Semiconductors Random-Access Memories. IEEE Transactions on Computers C-30(12), 982–985 (1981)

    Article  Google Scholar 

  5. Abadir, M.S., Reghbati, J.K.: Functional Testing of Semiconductor Random Access Memories. ACM Computer Surveys 15(3), 175–198 (1983)

    Article  Google Scholar 

  6. Papachistou, C.A., Saghal, N.B.: An Improved Method for Detecting Functional Faults in Random-Access Memories. IEEE Trans. on Computers C-34(2), 110–116 (1985)

    Article  Google Scholar 

  7. Dekker, R., et al.: A Realistic Fault Model and Test Algorithms for Static Random Access Memories. IEEE Trans. on Computers 9(6), 567–572 (1990)

    MathSciNet  Google Scholar 

  8. Schanstra, I., van de Goor, A.J.: Industrial evaluation of Stress Combinations for March Tests Applied to SRAMs. In: Proc. IEEE Int. Test Conference, pp. 983–992 (1999)

    Google Scholar 

  9. van de Goor, A.J., de Neef, J.: Industrial Evaluation of DRAMs Tests. In: Proc. of Design Automation and Test in Europe, pp. 623–630 (1999)

    Google Scholar 

  10. Adams, D., Cooley, E.S.: Analysis of Deceptive Read Destructive Memory Fault Model and Recommended Testing. In: Proc. of IEEE NATW (1999)

    Google Scholar 

  11. Hamdioui, S., van de Goor, A.J.: Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests. In: Proc. of Ninth Asian Test Symposium, pp. 131–138 (2000)

    Google Scholar 

  12. Al-Ars, Z., van de Goor, A.J.: Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs. In: Proc. of Design Automation and Test in Europe, pp. 401–406 (2001)

    Google Scholar 

  13. Hamdioui, S., Al-ars, Z., van de Goor, A.J.: Testing Static and Dynamic Faults in Random Access Memories. In: Proc. of IEEE VLSI Test Symposium, pp. 395–400 (2002)

    Google Scholar 

  14. Hamdioui, S., van de Goor, A.J., Reyes, J.R., Rodgers, M.: Memory Test Experiment: Industrial Results and Data. IEE Proceedings of Computers and Digital Techniques 153(1), 1–8 (2006)

    Article  Google Scholar 

  15. Hamdioui, S., et al.: Importance of Dynamic Faults for New SRAM Technologies. In: Proc. of European Test Workshop, pp. 29–34 (2003)

    Google Scholar 

  16. Hamdioui, S., Wadsworth, R., Reyes, J.D., Van De Goor, A.J.: Memory Fault Modeling Trends: A Case Study. Journal of Electronic Testing 20(3), 245–255 (2004)

    Article  Google Scholar 

  17. Dilillo, L., et al.: Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. In: Proc. Ninth IEEE European Test Symposium, pp. 140–145 (2004)

    Google Scholar 

  18. Van de Goor, A.J., Hamdioui, S., Wadsworth, R.: Detecting faults in the peripheral circuits and an evaluation of SRAM tests. In: Proc. of Inter. Test Conference, pp. 114–123 (2004)

    Google Scholar 

  19. Dilillo, L., et al.: Resistive-Open Defect Influence in SRAM Pre-Charge Circuit: Characterization and Analysis. In: 10th European Test Symposium on IEEE ETS 2005 (2005)

    Google Scholar 

  20. Hamdioui, S., Al-Ars, Z., van de Goor, A.J.: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. on Computers 55(11), 1630–1639 (2006)

    Article  Google Scholar 

  21. Dilillo, L., et al.: ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. Jour of Electronic Testing: Theory and Applications 22(3), 287–296 (2006)

    Article  Google Scholar 

  22. Hamdioui, S., Al-Ars, Z., Jimenez, J., Calero, J.: PPM Reduction on Embedded Memories in System on Chip. In: IEEE Proc. of European Test Symposium, Freiburg, Germany, pp. 85–90 (May 2007)

    Google Scholar 

  23. Al-Ars, Z., Hamdioui, S., Gaydadjiev, G.N., Vassiliadis, S.: Test Set Development for Cache Memory in Modern Microprocessors. IEEE Trans. Very Large Scale Integration (VLSI) Systems 16(6), 725–732 (2008)

    Article  Google Scholar 

  24. Powell, T., Kumar, A., Rayhawk, J., Mukherjee, N.: Chasing Subtle Embedded RAM Defects for Nanometer Technologies. In: Proc. of the IEEE Int. Test Conf., paper 33.4, vol. 23(5) (October 2007)

    Google Scholar 

  25. Mukherjee, N., Pogiel, A., Rajski, J., Tyszer, J.: High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 29, 441–453 (2010)

    Article  Google Scholar 

  26. Bhavnagarwala, A., et al.: The semiconductor industry in 2025. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 534–535 (2010)

    Google Scholar 

  27. van de Goor, A.J.: Testing Semiconductor Memories, Theory and Practice, 2nd edn. ComTex Publishing, Gouda (1998)

    Google Scholar 

  28. Nair, R.: An Optimal Algorithm for Testing Stuck-at Faults Random Access Memories. IEEE Trans. on Computers C-28(3), 258–261 (1979)

    Article  Google Scholar 

  29. Marinescu, M.: Simple and Efficient Algorithms for Functional RAM Testing. In: Proc. of IEEE International Test Conference, pp. 236–239 (1982)

    Google Scholar 

  30. De Jonge, J.H., Smeulders, A.J.: Moving Inversions Test Pattern is Thorough, Yet Speedy. In: Comp. Design, pp. 169–173 (1979)

    Google Scholar 

  31. van de Goor, A.J., Al-Ars, Z.: Functional fault models: A formal notation and taxonomy. In: Proc. IEEE VLSI Test Symp., pp. 281–289 (2000)

    Google Scholar 

  32. Hamdioui, S., van de Goor, A.J., Rodgers, M.: March SS: A Test for All Static Simple RAM Faults. In: Proc. of IEEE International Workshop on Memory Technology, Design, and Testing, Bendor, France, pp. 95–100 (2002)

    Google Scholar 

  33. Harutunvan, G., Vardanian, V.A., Zorian, Y.: Minimal March tests for unlinked static faults in random. In: Proc. of IEEE VLSI Test Symposium, pp. 53–59 (2005)

    Google Scholar 

  34. van de Goor, A.J., Hamdioui, S., Gaydadjiev, G.N., Al-Ars, Z.: New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. In: 18th IEEE Asian Test Symposium, Taichung, Taiwan, pp. 391–397 (November 2009)

    Google Scholar 

  35. van de Goor, A.J., et al.: March LA: A test for linked memory faults. In: Eur. Design Test Conf., p. 627 (1999)

    Google Scholar 

  36. Hamdioui, S., et al.: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5), 737–757 (2004)

    Article  Google Scholar 

  37. Hamdioui, S., et al.: A New Test Paradigm for Semiconductor Memories in the Nano-Era. In: Proc. of Asian Test Symposium, pp. 347–352 (2011)

    Google Scholar 

  38. McAnney, et al.: Random Testing for Stuck-At Storage Cells in an Embedded Memory. In: Proc. of Intern. Test Conference, pp. 157–166 (1984)

    Google Scholar 

  39. David, R., Fuentes, A., Courtois, B.: Random Patterns Testing Versus Deterministic Testing of RAMs. IEEE Trans. on Computers 5, 637–650 (1989)

    Article  Google Scholar 

  40. Dekker, R., Beenker, F., Thijssen, L.: Realistic built-in self-test for static RAMs. Design & Test of Computers 6(1), 26–34 (1989)

    Article  Google Scholar 

  41. Dreibelbis, J.H., Hedberg, E.L., Petrovic, J.G.: Built-In Self-Test for Integrated Circuits, US Patent, Number 5,173,906 (December 22, 1992)

    Google Scholar 

  42. Zarrineh, K., et al.: A new framework for generationg optimal March tests for memeory arrays. In: Proc. of the Int. Test Conf., pp. 73–82 (1998, 2001)

    Google Scholar 

  43. Powell, T.J., et al.: BIST for Deep Submicron ASIC Memories with High Performance Application. In: Proc. of the IEEE Int. Test Conf., pp. 386–392 (2003)

    Google Scholar 

  44. Appello, D., et al.: Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. In: Int. Test Conference, p. 379 (2003)

    Google Scholar 

  45. Aitken, R.C.: A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. In: Proc. of the IEEE Int. Test Conf., paper 35.2, pp. 997–1005 (2004)

    Google Scholar 

  46. Du, X., Mukherjee, N., Cheng, T.M.: Full-Speed Field-Programmable Memory BIST Architecture. In: Proc. of the IEEE Int. Test Conf., paper 45.3 (2005)

    Google Scholar 

  47. Du, X., Mukherjee, N., Cheng, W.-T., Reddy, S.M.: A Field-Programmable Memory BIST Architecture Supporting Algorithms and Multiple Nested Loops. In: Proc. of the Asian Test Symposium, paper 45.3 (2006)

    Google Scholar 

  48. van de Goor, A.J., Jung, C., Gaydadjiev, G.: Low-cost, Flexible SRAM MBIST Engine. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (April 2010)

    Google Scholar 

  49. van de Goor, A.J., Hamdioui, S., Gaydadjiev, G., Alars, Z.: Generic March Element Based Memory Built-In Self-Test, Dutch Patent Application; Filing Number NL 2004407, Filed date (January 2010)

    Google Scholar 

  50. van de Goor, A.J., Hamdioui, S., Kukner, H.: Generic, orthogonal and low-cost March Element based memory BIST. In: Inter. Test Conference, pp. 1–10 (2011)

    Google Scholar 

  51. Khare, J.B., Shah, A.B., Raman, A., Rayas, G.: Embedded Memory Field returns - Trials and Tribulations. In: Proc. IEE Int. Test Conf., Paper 26.3 (2006)

    Google Scholar 

  52. Borkar, S.: Design and Test Challenges for 32 nm and Beyond. Keynote speech at IEEE International Test Conference, p. 13 (2009)

    Google Scholar 

  53. Hamdioui, S., Al-Ars, Z., Mhamdi, L., Gaydadjiev, G.N., Vassiliadis, S.: Trends in Tests and Failure Mechanisms in Deep Sub-micron Technologies. In: IEEE Proc. of Int. Conference on Design and Test of Integrated Systems in Nanoscale Technology, pp. 216–221 (September 2006)

    Google Scholar 

  54. Vermeulen, B., Hora, C., Kruseman, B., Marinissen, E.J., van Rijsinge, R.: Trends in Testing Integrated Circuits. In: Proc. IEEE Int’l Test Conf., pp. 688–697 (2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Engineering Lab, Delft Univeristy of Technology, Mekelweg 4, 2628CD, Delft, The Netherlands

    Said Hamdioui

Authors
  1. Said Hamdioui
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Faculty of Informatics, Masaryk University, Botanická 68a, 602 00, Brno, Czech Republic

    Antonín Kučera

  2. Institute of Science and Technology Austria, Am Campus 1, 3400, Klosterneuburg, Austria

    Thomas A. Henzinger

  3. Faculty of Mathematics and Physics, Charles University in Prague, Malostranské nám. 25, 118 00, Praha 1, Czech Republic

    Jaroslav Nešetřil

  4. Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Brno, Czech Republic

    Tomáš Vojnar

  5. Institute of Computer Science, Masaryk University, Botanicka 68a, 602 00, Brno, Czec Republic

    David Antoš

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Hamdioui, S. (2013). Testing Embedded Memories: A Survey. In: Kučera, A., Henzinger, T.A., Nešetřil, J., Vojnar, T., Antoš, D. (eds) Mathematical and Engineering Methods in Computer Science. MEMICS 2012. Lecture Notes in Computer Science, vol 7721. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36046-6_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-36046-6_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36044-2

  • Online ISBN: 978-3-642-36046-6

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation