Abstract
The Advanced Encryption Standard, AES, is commonly used to provide data confidentiality and authentication in several security systems. Designing efficient hardware architecture with small hardware resource usage is a challenge. In this paper, a new technique for the FPGA implementation of the Subbyte and MixColumn transformations, an important part of AES, is introduced. Sub-byte transformation in AES is operated using S-box for each byte. The hardware complexity in AES is dominated by AES substitution box (S-box). S-box is considered as one of the most complicated and costly part of the system due to its non-linear structure. It has high power consumption and high design complexity. In this paper, S-box is optimized by using multiplexer logic design. It is compared to the typical ROM based lookup table and the combinational logic designs. The MixColumn is also optimised by shifting the bytes and reusing the resources. This is also done using the multiplexer logic.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
National Institute of Standards and Technology (U.S.), Advanced Encryption Standard, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
Reddy, S.K., Sakthivel, R., Praneeth, P.: VLSI Implementation of AES Crypto Processor for High Throughput. International Journal of Advanced Engineering Sciences and Technologies 6(1), 022–026 (2011)
Xinmiao, Z., Parhi, K.K.: High-speed VLSI architectures for the AES algorithm. IEEE Trans. on VLSI Systems 12, 957–967 (2004)
Ahmad, N., Hasan, R., Jubadi, W.M.: Design of AES S-Box using combinational logic optimization. In: IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), Penang, Malaysia, October 3-5 (2010)
Rachh, R.R., Ananda Mohan, P.V.: Implementation of AES S-Boxes using combinational logic. In: IEEE International Symposium on Circuits and Systems, pp. 3294–3297 (2008)
Kim, M., Kim, J., Choi, Y.: Low Power Architecture of AES Crypto Module for Wireless Sensor Network. World Academy of Science, Engineering and Technology (2005)
Ahmad, E.G., Shaaban, E., Hashem, M.: Lightweight MixColumns Implementation for AES. In: Proceedings of the 9th WSEAS International Conference on Applied Informatics and Communications, pp. 253–258
Noo-intara, P., Chantarawong, S., Choomchuay, S.: Architectures for Mix-Column Transform for the AES. In: ICEP (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rahimunnisa, K., Priya Zach, M., Suresh Kumar, S., Jayakumar, J. (2012). Efficient Techniques for the Implementation of AES SubByte and MixColumn Transformations. In: Meghanathan, N., Nagamalai, D., Chaki, N. (eds) Advances in Computing and Information Technology. Advances in Intelligent Systems and Computing, vol 176. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31513-8_51
Download citation
DOI: https://doi.org/10.1007/978-3-642-31513-8_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31512-1
Online ISBN: 978-3-642-31513-8
eBook Packages: EngineeringEngineering (R0)