Abstract
SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory.
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References
Allen, G., Swift, G., Carmichael, C.: Virtex-4 VQ static SEU characterization summary. Jet Propulsion Laboratory, Pasadena, CA. National Aeronautics and Space Administration (2008)
Sonza Reorda, M., Sterpone, L., Violante, M.: Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. In: European Test Symposium, pp. 136–141. IEEE Computer Society, Los Alamitos (2005)
Quinn, H., Morgan, K., Graham, P., Krone, J., Caffrey, M., Lundgreen, K.: Domain crossing errors: Limitations on single device triple-modular redundancy circuits in Xilinx FPGAs. IEEE Transactions on Nuclear Science 54(6), 2037–2043 (2007)
Ostler, P.S., Caffrey, M.P., Gibelyou, D.S., Graham, P.S., Morgan, K.S., Pratt, B.H., Quinn, H.M., Wirthlin, M.J.: SRAM FPGA reliability analysis for harsh radiation environments. IEEE Transactions on Nuclear Science 56(6), 3519–3526 (2009)
Xilinx: SEU Strategies for Virtex-5 Device, http://www.xilinx.com/support/documentation/application_notes/xapp864.pdf
Lanuzza, M., Zicari, P., Frustaci, F., Perri, S., Corsonello, P.: A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi-Bit Upsets in SRAM-based FPGAs. In: IEEE International Symposium on Industrial Electronics, pp. 1989–1994. IEEE, Los Alamitos (2010)
Osterloh, B., Michalik, H., Habinc, S.A., Fiethe, B.: Dynamic partial reconfiguration in space applications. In: NASA/ESA Conference on Adaptive Hardware and Systems, pp. 336–343. IEEE, Los Alamitos (2009)
Xilinx: Correcting Single-Event Upsets with a Self-Hosting Configuration Management Core, http://www.xilinx.com/support/documentation/application_notes/xapp989.pdf
Heiner, J., Collins, N., Wirthlin, M.: Fault tolerant ICAP controller for high-reliable internal scrubbing. In: IEEE Aerospace Conference, pp. 1–10. IEEE, Los Alamitos (2008)
Berg, M., Poivey, C., Petrick, D., Espinosa, D., Lesea, A., LaBel, K.A., Friendlich, M., Kim, H., Phan, A.: Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis. IEEE Transactions on Nuclear Science 55(4), 2259–2266 (2008)
Berg, M.: The NASA Goddard space flight center radiation effects and analysis group Virtex 4 scrubber. In: Xilinx Radiation Test Consortium (XRTC) Meeting (2007)
Xilinx: Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory, http://www.xilinx.com/support/documentation/application_notes/xapp1088.pdf
Quinn, H., Morgan, K., Graham, P., Krone, J., Caffrey, M.: A review of Xilinx FPGA architectural reliability concerns from Virtex to Virtex-5. In: 9th European Conference on Radiation and Its Effects on Components and Systems, pp. 1–8. IEEE, Los Alamitos (2007)
Adell, P., Allen, G.: Assessing and mitigating radiation effects in Xilinx FPGAs. Jet Propulsion Laboratory, Pasadena, CA. California Institute of Technology (2008)
Herrera-Alzu, I., López-Vallejo, M.: Cycle-Accurate Configuration Layer Model for Xilinx Virtex FPGAs. In: 13th European Conference on Radiation and Its Effects on Components and Systems. IEEE, Los Alamitos (2011)
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Herrera-Alzu, I., López-Vallejo, M. (2011). Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. In: Ayala, J.L., García-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_14
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DOI: https://doi.org/10.1007/978-3-642-24154-3_14
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