Abstract
The transition from combinational to sequential networks is explained step by step, starting from a simple gate with feedback and arriving to the structure and behavior of the principal types of flip-flops. They are classified according to their temporal response (direct command, level enabled, master–slave, and edge triggered) and the logical operation (SR, D, JK). The timing parameters of physically implemented devices are considered. The chapter introduces the concept and techniques for synchronization that will be further examined in the following ones.
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Notes
- 1.
The transition can be “positive” (from 0 to 1, or “rising edge”) or “negative” (from 1 to 0, the “falling edge”).
- 2.
In large-scale integration devices that use a high number of flip-flops, the designer takes great care with the physical connections of the clock to avoid time misalignments among the various elements of the network. Logical gates along the clock path are also invalid.
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© 2019 Springer International Publishing AG, part of Springer Nature
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Donzellini, G., Oneto, L., Ponta, D., Anguita, D. (2019). Introduction to Sequential Networks. In: Introduction to Digital Systems Design. Springer, Cham. https://doi.org/10.1007/978-3-319-92804-3_5
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DOI: https://doi.org/10.1007/978-3-319-92804-3_5
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-92803-6
Online ISBN: 978-3-319-92804-3
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