Skip to main content

Alternative Logic Families for Energy-Efficient and High Performance Chip Design

  • Chapter
  • First Online:

Part of the book series: NanoScience and Technology ((NANO))

Abstract

With advances in technology and the expansion of mobile applications, energy consumption, which is one of the fundamental limits in both high performance microprocessors and low to medium performance portable systems.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   99.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. J.M. Rabaey, Low power design essentials (Springer Science and Business Media, 2009)

    Google Scholar 

  2. K. Roy, S. Prasad, Low-power CMOS VLSI circuit design (Wiley India, 2009)

    Google Scholar 

  3. J. Rabaey, M. Pedram, P. Landman, Low Power Design Methodologies (Kluwer Academic Publishers, Boston, 1995)

    Google Scholar 

  4. M. Keating, D. Flynn, R. Aitken, A. Gibbons, K. Shi, Low power methodology manual for system-on-chip design pp. 33–100

    Google Scholar 

  5. B. Calhoun, Y. Cao, X. Li, K. Mai, L. Pileggi, R. Rutenbar, K. Shepard, Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proc. IEEE 96(2), 343–365 (2008)

    Article  Google Scholar 

  6. B. Calhoun, J. Bolus, S. Khanna, A. Jurik, A. Weaver, T. Blalock, Sub-threshold operation and cross-hierarchy design for ultra low power wearable sensors. in ISCAS ’09, pp. 1437–1440, May (2009)

    Google Scholar 

  7. M. Pedram, S. Nazarian, Thermal modeling, analysis, and management in VLSI circuits: principles and methods. Proc. IEEE 94(8), 1487–1501 (2006)

    Article  Google Scholar 

  8. A. Wang, A. Chandrakasan, A 180 mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid State Circuits 40(1), 310–319 (2005)

    Article  Google Scholar 

  9. L. Alarcon, T. Liu, M. Pierson, J. Rabaey, Exploring very low-energy logic: a case study. J. Low Power Electron. 3(3), 22–233 (2007)

    Article  Google Scholar 

  10. L. Benini, G. De Micheli, State assignment for low power dissipation. IEEE J. Solid-State Circuits 30, 258–268 (1995)

    Article  Google Scholar 

  11. Y. Xia, A.E.A. Almaini, Genetic algorithm based state assignment for power and area optimization. IEE Proc.Comput. Digital Tech. 149, 128–133 (2002)

    Article  Google Scholar 

  12. L. Xie, P. Qiu, Q. Qiu, Partitioned bus coding for energy reduction in, in Proceedings of the ASP-DAC Design Automation Conference, vol.2 (Asia and South Pacific, 2005), pp. 1280−1283

    Google Scholar 

  13. B.H. Calhoun, A.P. Chandrakasan, Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering. IEEE J. Solid-State Circuits 41, 238–245 (2006)

    Article  Google Scholar 

  14. B. Zhai, D. Blaauw, D. Sylvester, K. Flautner, The limit of dynamic voltage scaling and insomniac dynamic voltage scaling, very large scale integration (VLSI) systems. IEEE Trans. 13, 1239–1252 (2005)

    Google Scholar 

  15. J. Shinde, S.S. Salankar, Clock gating—A power optimizing technique for VLSI circuits, in Annual IEEE India Conference, (INDICON, 2011), pp. 1−4

    Google Scholar 

  16. L. Li, W. Wang, K. Choi, S. Park, M.K. Chung, SeSCG: selective sequential clock gating for ultra-low-power multimedia mobile processor design, in IEEE International Conference on Electro/Information Technology, (EIT), pp. 1−6

    Google Scholar 

  17. W. Shen, Y. Cai, X. Hong, J. Hu, An effective gated clock tree design based on activity and register aware placement, very large scale integration (VLSI) systems. IEEE Trans. 18, 1639–1648 (2010)

    Google Scholar 

  18. H. Mahmoodi, V. Tirumalashetty, M. Cooke, K. Roy, Ultra low-power clocking scheme using energy recovery and clock gating, very large scale integration (VLSI) systems. IEEE Trans. 17, 33–44 (2009)

    Google Scholar 

  19. R. Bhutada, Y. Manoli, Complex clock gating with integrated clock gating logic cell, in DTIS International Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp. 164−169 (2007)

    Google Scholar 

  20. P.K. Pal, R.S. Rathore, A.K. Rana, G. Saini, New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper, in 2010 International Conference on Computer and Communication Technology (ICCCT), pp. 296−301 (2010)

    Google Scholar 

  21. S. Dropsho, E.G. Friedman, Managing static leakage energy in microprocessor functional units, in Proceedings 35th Annual IEEE/ACM International Symposium onMicroarchitecture, 2002.(MICRO-35), pp. 321–332 (2002)

    Google Scholar 

  22. S. Badel, Y. Leblebici, Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS, pp. 1871−1874

    Google Scholar 

  23. A. Inoue, V.G. Dklobdzija, W.W. Walker, M. Kai, T. Izawa, A low power SOI adder using reduced-swing charge recycling circuits, in 2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. pp. 316−317, 459 (2001)

    Google Scholar 

  24. H. Keil, M. Momeni, A. Guntoro, A.G. Ortiz, M. Glesner, A novel leakage-estimation method for input-vector control, in IEEE Asia Pacific Conference on Circuits and Systems, APCCAS, pp. 570−573 (2008)

    Google Scholar 

  25. S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim, K. Roy, Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. on Very Large Scale Integr. (VLSI) Syst. 11(4) (2003)

    Google Scholar 

  26. J.P. Halter and F.N. Najm, A gate-level leakage power reduction method for ultra-low-power CMOS circuits, in IEEE Curctom Integrated circuits conference, pp. 475−478 (1997)

    Google Scholar 

  27. J. Kuo, H. Wang, A 24 GHz CMOS power amplifier using reversed body bias technique to improve linearity and power added efficiency, in 2012 IEEE MTT-S International Microwave Symposium Digest (MTT), pp. 1−3 (2012)

    Google Scholar 

  28. L. Xiao, C. Liu, Y. Sun, A novel adaptive reverse body bias technique to minimize standby leakage power and compensate process and temperature variations. Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC) 2011, 1565–1568 (2011)

    Article  Google Scholar 

  29. K. K. Kim, Y. B. Kim, Optimal Body Biasing for Minimum Leakage Power in Standby Mode, in IEEE International SymposiumCircuits and Systems, ISCAS, pp. 1161−1164 May (2007)

    Google Scholar 

  30. H. Jeon, Y. B. Kim, M. Choi, A novel technique to minimize standby leakage power in nanoscale CMOS VLSI, in I2MTC ’09, pp. 1372−1375 (2009)

    Google Scholar 

  31. H.S. Won, K.S. Kim, K.O. Jeong, K.T. Park, K.M. Choi, J.T. Kong, An MTCMOS design methodology and its application to mobile computing, in ISLPED ‘03, pp. 110−115 (2003)

    Google Scholar 

  32. Z. Liu, V. Kursun, Characterization of wake-up delay versus sleep mode power consumption and sleep/active mode transition energy overhead tradeoffs in MTCMOS circuits, in MWSCAS ’08, pp. 362−365, Aug (2008)

    Google Scholar 

  33. A.P. Chandrakasan, S. Sheng, R.W. Brodersen, Low-power CMOS digital design. IEEE J. Solid-State Circuits 27, 473–484 (1992)

    Article  Google Scholar 

  34. G. Schrom, S. Selberherr, Ultra-low-power CMOS technologies. in International Semiconductor Conference (CAS) Digest of Technical Papers, pp. 237−246 (1996)

    Google Scholar 

  35. A.P. Chandrakasan, R.W. Brodersen, Minimizing power consumption in digital CMOS circuits. Proc. IEEE 83, 498–523 (1995)

    Article  Google Scholar 

  36. S. Kang, Elements of low power design for integrated systems, in ISLPED ’03, August (2003)

    Google Scholar 

  37. A. Wang, B. H. Calhoun, A. Chandrakasan, Sub-threshold design for ultra low-power systems (Springer publishers, 2005)

    Google Scholar 

  38. N. Verma, A. Chandrakasan, A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy. IEEE J. Solid State Circuits 43(1), 141–149 (2008)

    Article  Google Scholar 

  39. D. Bol, D. Kamel, D.S Flandre, J.D. Legat, Nanometer MOSFET Effects on the Minimum-Energy Point of 45 nm Subthreshold Logic, in ISLPED ’09, pp. 3−8, Aug (2009)

    Google Scholar 

  40. R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS vs pass-transistor logic. IEEE J. Solid-State Circuits 32, 1079–1090 (1997)

    Article  Google Scholar 

  41. M. Anis, M. Allam, and M. Elmasry, Impact of technology scaling on CMOS logic styles, IEEE Trans. Circuits Syst. II Analog Digital Sig. Process. 49(8), pp. 577,588 (2002)

    Google Scholar 

  42. S. Hsiao, M. Tsai, C. Wen, Transistor sizing and layout merging of basic cells in pass transistor logic cell library, in IEEE International Symposium on VLSI Design, Automation and Test, 2008. VLSI-DAT 2008, pp. 89−92, 23−25 April (2008)

    Google Scholar 

  43. M.W. Allam, M.H. Anis, M.I. Elmasry, High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies, in 2000 IEEE International Symposium on Low Power Electronics and Design, ISLPED ‘00, pp. 155−160, (2000)

    Google Scholar 

  44. N.F. Goncalves, H. De Man, NORA: a racefree dynamic CMOS technique for pipelined logic structures. IEEE J. Solid-State Circuits 18, 261–266 (1983)

    Article  Google Scholar 

  45. H. Razak, High performance ASIC design: using synthesizable domino logic in an ASIC flow (Cambridge University Press, 2008)

    Google Scholar 

  46. R.G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-threshold computing: reclaiming moore’s law through energy efficient integrated circuits. Proc. IEEE 98, 253–266 (2010)

    Article  Google Scholar 

  47. N. Weste, K. Eshraghian, Principles of CMOS digital design, (Addison-Wesley, pp. 304−307)

    Google Scholar 

  48. S. Hendrawan, K. Roy, B.C. Paul, Robust subthreshold logic for ultra-low power operation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 9(1), 90–99 (2001)

    Article  Google Scholar 

  49. K. Yano, Y. Sasaki, K. Rikino, K. Seki, Top-down pass-transistor logic design. IEEE J. Solid-State Circuits 31(6), pp. 792−803 (1996)

    Google Scholar 

  50. A. Morgenshtein, A. Fish, A. Wagner, Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology, in Proceedings 14th Annual IEEE International ASIC/SOC Conference, 2001, pp. 39−43 (2001)

    Google Scholar 

  51. A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI)—a technique for low power design of digital circuits: analysis and characterization, in ISCAS 2002 IEEE International Symposium on Circuits and Systems 2002, 1,pp. I−477-I−480 (2002)

    Google Scholar 

  52. A. Morgenshtein, I. Shwartz, and A. Fish. Gate diffusion input (GDI) logic in standard CMOS nanoscale process.in 2010 IEEE 26th Convention of. IEEE Electrical and Electronics Engineers in Israel (IEEEI) (2010)

    Google Scholar 

  53. V. Sze, A.P. Chandrakasan, A 0.4-V UWB baseband processor, in 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 262−267 (2007)

    Google Scholar 

  54. A. Morgenshtein et al., Full-swing gate diffusion input logic—Case-study of low-power CLA adder design. Integr. VLSI J. 47(1), 62–70 (2014)

    Article  Google Scholar 

  55. B. Nikolic et al., Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid-State Circuits 35(6), 876–884 (2000)

    Article  Google Scholar 

  56. K. Tiri, M. Akmal, I. Verbauwhede. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. in Proceedings of the 28th European IEEE, Solid-State Circuits Conference, 2002. ESSCIRC (2002)

    Google Scholar 

  57. G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M. Chen, Z. Foo, D. Sylvester, D. Blaauw, Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells, in 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 288−289 (2010)

    Google Scholar 

  58. A. Asenov, A.R. Brown, J.H. Davies, S. Kaya, G. Slavcheva, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs. Electron Devices, IEEE Transactions on 50, 1837–1852 (2003)

    Article  Google Scholar 

  59. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91, 305–327 (2003)

    Article  Google Scholar 

  60. A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, C.H. Kim, Leakage power analysis and reduction for nanoscale circuits. Micro IEEE 26, 68–80 (2006)

    Article  Google Scholar 

  61. J. Kao, S. Narendra, A. Chandrakasan, Subthreshold leakage modeling and reduction techniques, in IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002, pp. 141−148 (2002)

    Google Scholar 

  62. B. Zhai, S. Hanson, D. Blaauw, D. Sylvester, Analysis and mitigation of variability in subthreshold design, in Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. ISLPED ‘05, pp. 20−25 (2005)

    Google Scholar 

  63. D. Bol, R. Ambroise, D. Flandre, J. Legat, Analysis and minimization of practical energy in 45 nm subthreshold logic circuits, in IEEE International Conference on Computer Design, 2008. ICCD 2008, pp. 294−300 (2008)

    Google Scholar 

  64. H. Kim, K. Roy, Ultra-low power DLMS adaptive filter for hearing aid applications. Low power electronics and design, international Symposium on 2001, 352–357 (2001)

    Google Scholar 

  65. H. Kaul, M.A. Anders, S.K. Mathew, S.K. Hsu, A. Agarwal, R.K. Krishnamurthy, S. Borkar, A 320 mV 56 μW 411 GOPS/Watt ultra-low voltage motion estimation accelerator in 65 nm CMOS. IEEE J. Solid-State Circuits 44, 107–114 (2009)

    Article  Google Scholar 

  66. Y. Lin, D. Sylvester, D. Blaauw, A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems, in IEEE Custom Integrated Circuits Conference, 2007. CICC ‘07, pp. 397−400 (2007)

    Google Scholar 

  67. H. Soeleman, K. Roy, B. Paul, Robust ultra-low power sub-threshold DTMOS logic, in Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000. ISLPED ‘00, pp. 25−30 (2000)

    Google Scholar 

  68. M. Penney, L. Lau, MOS Integrated Circuits, pp. 260−182 (1972)

    Google Scholar 

  69. J.M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital integrated circuits: a design perspective. ch. 4 (Upper Saddle River, N.J.: Pearson Education, 2003), p. 222

    Google Scholar 

  70. H. Soeleman, K. Roy, B. Paul, Sub-domino logic: ultra-low power dynamic sub-threshold digital logic, in Proceedings of the 2000 International Symposium on VLSI Design, 2001, pp. 211−214 (2001)

    Google Scholar 

  71. D. Harris, M.A. Horowitz, Skew-tolerant domino circuits. IEEE J. Solid-State Circuits 32, 1702–1711 (1997)

    Article  Google Scholar 

  72. H. Soeleman, K. Roy, Ultra-low power digital subthreshold logic circuits, in Proceedings 1999 International Symposium on Low Power Electronics and Design 1999, pp. 94−96 (1999)

    Google Scholar 

  73. S. Thompson, I. Young, J. Greason, M. Bohr, Dual threshold voltages and substrate bias: keys to high performance, low power, 0.1 & mu;m logic designs, in 1997 Symposium on VLSI Technology, 1997 Digest of Technical Papers. pp. 69−70 (1997)

    Google Scholar 

  74. M.W. Allam, M.H. Anis, M.I. Elmasry, High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies, in Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000. ISLPED ‘00. pp. 155−160 (2000)

    Google Scholar 

  75. K. Yano, Y. Sasaki, K. Rikino, K. Seki, Top-down pass-transistor logic design. IEEE J. Solid-State Circuits 31, 792–803 (1996)

    Article  Google Scholar 

  76. M. Alioto, G. Palumbo, Design strategies for source coupled logic gates. Circuits and Systems I: Fundamental Theory and App. IEEE Trans. 50, 640–654 (2003)

    Article  Google Scholar 

  77. A. Tajalli, E.J. Brauer, Y. Leblebici, E. Vittoz, Subthreshold source-coupled logic circuits for ultra-low-power applications. IEEE J. Solid-State Circuits 43, 1699–1710 (2008)

    Article  Google Scholar 

  78. A. Kaizerman, S. Fisher, A. Fish, Subthreshold dual mode logic, very large scale integration (VLSI) systems. IEEE Trans. 21, 979–983 (2013)

    Google Scholar 

  79. I. Levi, A. Kaizerman, A. Fish, Low voltage dual mode logic: model analysis and parameter extraction. Microelectronics Journal, Elsevier 44(6), 553–560 (2013)

    Article  Google Scholar 

  80. I. Levi, A. Belenky, A. Fish, Logical effort for CMOS based dual mode logic (DML) gates. IEEE Trans. VLSI Syst. 22(5), 1042–1053 (2014)

    Article  Google Scholar 

  81. M. Elgebaly, M. Sachdev, Efficient adaptive voltage scaling system through on-chip critical path emulation, in Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004. ISLPED ‘04, pp. 375−380 (2004)

    Google Scholar 

  82. J. M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital integrated circuits: a design perspective, ch. 4, (Upper Saddle River, N.J.: Pearson Education, 2003), p. 222

    Google Scholar 

  83. I.E. Sutherland, B. Sproull, D. Harris, Logical Effort—Designing Fast CMOS Circuits (Morgan Kaufmann, San Mateo, CA, 1999)

    Google Scholar 

  84. S.P. Mohanty, N. Ranganathan, E. Kougianos, P. Patra, Low-power high-level synthesis for nanoscale CMOS circuits, (Springer, 2008)

    Google Scholar 

  85. T. Sasao, Switching theory for logic synthesis, (Kluwer Academic Publishers, 1999)

    Google Scholar 

  86. Y. Kukimoto, M. Berkelaar, K. Sakallah, Static timing analysis, Logic Synthesis and Verification, pp. 373−401 (2002)

    Google Scholar 

  87. J.J. Zasio, K.C. Choy, D.R. Parham, Static timing analysis of semiconductor digital circuits (1990)

    Google Scholar 

  88. H.L.A. Chen, E.K.W. Loo, J.B. Kuo, M.J. Syrzycki, Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90 nm MTCMOS Technology, in Canadian Conference on Electrical and Computer Engineering, 2007. CCECE 2007, pp. 1671−1674 (2007)

    Google Scholar 

  89. N. Sirisantana, L. Wei, K. Roy, High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness, in Proceedings 2000 International Conference on Computer Design, 2000, pp. 227−232 (2000)

    Google Scholar 

  90. M. Meijer, J.P. de Gyvez, Body-bias-driven design strategy for area-and performance-efficient CMOS circuits,very large scale integration (VLSI) systems. IEEE Trans. 20, 42–51 (2012)

    Google Scholar 

  91. X. Liu, S. Mourad, Performance of submicron CMOS devices and gates with substrate biasing, in Proceedings ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Circuits and Systems, 2000, vol. 4, pp. 9−12 (2000)

    Google Scholar 

  92. A. Mokhov, D. Sokolov, A. Yakovlev, Adapting asynchronous circuits to operating conditions by logic parametrization, in 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 17−24 (2012)

    Google Scholar 

  93. I. Levi, O. Bass, A. Kaizerman, A. Belenky, A. Fish, High speed dual mode logic carry look ahead adder, in Proceedings IEEE International Symposium on Circuits and Systems (Seoul, Korea, May 2012) pp. 3037−3040

    Google Scholar 

  94. I. Levi, A. Albeck, A. Fish, S. Wimer, A low energy and high performance DM^2 adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61(11), 3175–3183 (2014)

    Article  Google Scholar 

  95. I. Koren, Computer arithmetic algorithms (Universities Press, 2002)

    Google Scholar 

  96. A.T. Tran and B.M. Baas, Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS, in 2010 Third International Conference on Communications and Electronics (ICCE), pp. 87−91 (2010)

    Google Scholar 

  97. M. Lehman, N. Burla, Skip techniques for high-speed carry-propagation in binary arithmetic Units, IRE Transactions on Electronic Computers, vol. EC-10, pp. 691−698 (1961)

    Google Scholar 

  98. S. Majerski, On determination of optimal distributions of carry skips in adders, IEEE Transactions on Electronic Computers, pp. 45−58 (1967)

    Google Scholar 

  99. A. Guyot, B. Hochet, J.M. Muller, A way to build efficient carry-skip adders. Comut. IEEE Trans. 100, 1144–1152 (1987)

    Article  MATH  Google Scholar 

  100. V.G. Oklobdzija and E.R. Barnes, Some optimal schemes for ALU implementation in VLSI technology, in 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH), pp. 2−8 (1985)

    Google Scholar 

  101. K.S. Kundert, P. Foreword By-Gray, The designer’s guide to SPICE and SPECTRE (Kluwer Academic Publishers, 1995)

    Google Scholar 

  102. D. Markovic, C.C. Wang, L.P. Alarcon, T. Liu, J.M. Rabaey, Ultralow-power design in near-threshold region. Proc. IEEE 98, 237–252 (2010)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Itamar Levi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Levi, I., Fish, A. (2017). Alternative Logic Families for Energy-Efficient and High Performance Chip Design . In: Eisenstein, G., Bimberg, D. (eds) Green Photonics and Electronics. NanoScience and Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-67002-7_6

Download citation

Publish with us

Policies and ethics