Design of a DC/DC Controller IP in 28 nm

Abstract

Power management IPs become more and more attractive in deep sub-micron technologies in order to optimize the power efficiency of today’s complex chips demanding Amps of current. The development of a 28 nm analog buck DC/DC controller is presented here, showing the main design challenges and architectural choices. The main idea is to take advantage of technology scaling, so the controlling engine is purely digital, generating the discrete PWM driving signals to the off-chip power FETs. The analog circuits implement the voltage comparisons to set the output voltage level and the PWM signal buffering, which has to be realized in high voltage and with the correct timing. One of the main challenges of the analog design is presented by the requirement of a single input power supply with a wide range from 1.8 V − 5 % up to 3.3 V + 5 %, but just using 1.8 V compliant devices. Since the PWM modulator has to provide a full rail-to-rail output driving to the external FETs, an intense design phase and reliability analysis has been performed, accessing the foundry information and identifying the proper external low-gate-drive FETs. The analog layout implementation in 28 nm has to satisfy stringent rules with proper structure to guarantee that the device models match with the silicon performance, in particular for circuits where a precise signal sensing is critical. Measured results are available.