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Asynchronous Parallel Dijkstra’s Algorithm on Intel Xeon Phi Processor

How to Accelerate Irregular Memory Access Algorithm

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Algorithms and Architectures for Parallel Processing (ICA3PP 2018)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 11334))

Abstract

As the instruction-level parallelism (ILP) on CPU develops to a rather advanced level, the exploration that whether many-core architecture is applicable for graph algorithms is generating more interests in researchers. However, due to the irregular memory access and the low ratio of computation to memory access, the performance of graph algorithms on many-core architectures has never worked good enough.

To obtain outstanding speedup on many-core architecture, first of all, we need to figure out three questions: (i) how to optimize the memory access, (ii) how to minimize the overhead of synchronization, (iii) how to exploit the parallelism in algorithm. Prior works hardly reach the goal if such questions are treated in separated way. Throughout this paper, we aim to settle these questions systematically, and try to provide a set of methods of optimizing graph algorithms on many-core architecture.

This paper mainly discusses how to accelerate the Single Source Shortest Path (SSSP) problem on Intel Many Integrated Core (MIC) architecture, on which we propose an asynchronous parallel Dijkstra’s algorithm. It aims at maximizing parallelism and minimizing overhead of synchronization. Experimental result shows that the MIC architecture could efficiently solve the SSSP problem, and its performance could be sped up by 9.2x compared to the benchmark of DIMACS.

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Acknowledgments

This work is supported by National Key R&D Program of China (under Grant 2017YFB0202001) and National Natural Science Foundation of China (under Grants 61432018,61672208).

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Authors and Affiliations

  1. EECS of Peking University, Beijing, 100871, People’s Republic of China

    Weidong Zhang & Yifeng Chen

  2. HuaWei Inc., Shenzhen, China

    Lei Zhang

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  1. Weidong Zhang
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  2. Lei Zhang
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  3. Yifeng Chen
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Corresponding author

Correspondence to Yifeng Chen .

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Editors and Affiliations

  1. Rutgers University, Newark, NJ, USA

    Jaideep Vaidya

  2. Guangzhou University, Guangzhou, China

    Jin Li

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Zhang, W., Zhang, L., Chen, Y. (2018). Asynchronous Parallel Dijkstra’s Algorithm on Intel Xeon Phi Processor. In: Vaidya, J., Li, J. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2018. Lecture Notes in Computer Science(), vol 11334. Springer, Cham. https://doi.org/10.1007/978-3-030-05051-1_24

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  • DOI: https://doi.org/10.1007/978-3-030-05051-1_24

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  • Publisher Name: Springer, Cham

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  • Online ISBN: 978-3-030-05051-1

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