VHDL Specific Issues in High Level Synthesis

Abstract

VHDL is essentially a simulation language which is now tried to be used throughout the design process, not only for simulation but also for synthesis and test. High Level Synthesis methodology fits well to the idea of using a specification/simulation language like VHDL for the design of digital circuits. Unfortunately, obvious advantages of using one hardware language in the design process can be outweighed by the language incompatibility with some of the design tasks; incompatibility from the user as well as from the tool developer point of view. This paper analyses some essential features of VHDL as the synthesis language, points to problems and suggests practical solutions which do not demand changes in VHDL 1076 standard. Some questions of efficiency of the synthesis process are also raised that lead to requirements for changes or completions of present VHDL.