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Subthreshold MOS for Ultra-Low Power

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Abstract

This Chapter provides a brief review on modeling of MOSFET devices especially for weak-inversion (WI) devices.1 The main issues associated with WI design such as variation due to PVT, mismatch effects,and device noise are briey addressed. Meanwhile, a review on the main problems for implementing ULP CMOS circuits is provided. At the end of the Section, an analytical approach for systematic design of digital CMOS circuits operating in WI region with optimum energy consumption and acceptable reliability is proposed.

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Authors and Affiliations

  1. Microelectronic Systems Lab. (LSM), Ecole Polytechnique Fédérale de Lausanne (EPFL), Station 11, 1015, Lausanne, Switzerland

    Armin Tajalli & Yusuf Leblebici

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  1. Armin Tajalli
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  2. Yusuf Leblebici
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Correspondence to Armin Tajalli .

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Tajalli, A., Leblebici, Y. (2010). Subthreshold MOS for Ultra-Low Power. In: Extreme Low-Power Mixed Signal IC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6478-6_2

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  • DOI: https://doi.org/10.1007/978-1-4419-6478-6_2

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