Skip to main content
SpringerLink
Log in

A Tool to Schedule Parallel Applications on Multiprocessors: The NANOS CPU Manager

  • Conference paper
Job Scheduling Strategies for Parallel Processing (JSSPP 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1911))

Included in the following conference series:

Abstract

Scheduling parallel applications on shared– memory multiprocessors is a di.cult task that requires a lot of tuning from application programmers, as well as operating system developers and system managers. In this paper, we present the characteristics related to kernel– level scheduling of the NANOS environment and the results we are achieving. The NANOS environment is designed and tuned speci.cally to achieve high performance in current shared– memory multiprocessors. Taking advantage of the wide and e.cient dialog established between applications and the NANOS environment, we are designing powerful scheduling policies. The information exchanged ranges from simply communicating the number of requested processors to providing information of the current speedup achieved by the applications. We have devised several scheduling policies that use this interface, such as Equipartition, Variable Time Quantum DSS and Dynamic Performance Analysis. The results we have obtained with these policies indicate that there is a lot of work to do in the search for a – good– scheduling policy, which can include characteristics like sustainable execution times, fairness and throughput. For instance, we show through several experiments that ben- efits in execution time range from 15% to 100%, depending on the policy used and the characteristics of the workload.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. T. Anderson, B. Bershad, E. Lazowska and H. Levy, “Scheduler Activations: Effective Kernel Support for the User– Level Management of Parallelism≓, Proceedings of the 13th. ACM Symposium on Operating System Principles (SOSP), October 1991.

    Google Scholar 

  2. E. Ayguadé, X. Martorell, J. Labarta, M. Gonzàlez and N. Navarro, “Exploiting Parallelism Through Directives on the Nano-Threads Programming Model≓, Proceedings of the 10th.Workshop on Language and Compilers for Parallel Computing (LCPC), Minneapolis, USA, August 1997.

    Google Scholar 

  3. E. Ayguadé, X. Martorell, J. Labarta, M. Gonzàlez and N. Navarro, “Exploiting Multiple Levels of Parallelism in Shared– memory Multiprocessors: a Case Study≓, Dept. d’Arquitectura de Computadors-Universitat Politècnica de Catalunya, Technical Report: UPC-DAC-1998-48, November 1998.

    Google Scholar 

  4. E. Ayguadé, M. Gonzàlez, J. Labarta, X. Martorell, N. Navarro and J. Oliver, “NanosCompiler: A ResearchPlatform for OpenMP Extensions≓, Dept. d’Arquitectura de Computadors-Universitat Politècnica de Catalunya, Technical Report: UPC-DAC-1999-39, 1999.

    Google Scholar 

  5. D. Bailey, T. Harris, W. Saphir, R. Wijngaart, A. Woo and M. Yarrow, “The NAS Parallel Benchmarks 2.0≓, Technical Report NAS-95-020, NASA, December 1995.

    Google Scholar 

  6. A. Charlesworth, “STARFIRE: Extending the SMP Envelope≓, IEEE Micro, Jan/Feb 1998.

    Google Scholar 

  7. J. Corbalán, J. Labarta, “Dynamic Speedup Calculation through Self-Analysis≓, Dept. d’Arquitectura de Computadors-Universitat Politècnica de Catalunya, Technical Report: UPC-DAC-1999-43, 1999.

    Google Scholar 

  8. J. Corbalán, X. Martorell and J. Labarta, “A Processor Scheduler: The CpuManager≓, Dept. d’Arquitectura de Computadors-Universitat Politècnica de Catalunya, Technical Report: UPC-DAC-1999-69, 1999.

    Google Scholar 

  9. D. Craig, “An Integrated Kernel– and User– Level Paradigm for E.cient Multiprogramming Support≓, M.S. thesis, Department of Computer Science, University of Illinois at Urbana– Champaign, 1999.

    Google Scholar 

  10. M. Crovella, P. Das, C. Dubnicki, T. LeBlanc, E. Markatos, “Multiprogramming on Multiprocessors≓e, Technical Report 385, University of Rochester, February 1991 (revised May 1991).

    Google Scholar 

  11. Digital Equipment Corporation / Compaq Computer Corporation, “AlphaServer 8x00 Technical Summary≓, http://www.digital.com/alphaserver/alphasrv84008x00_summ.html, 1999.

  12. D.L. Eager, J. Zahorjan and E.D. Lazowska, “Speedup Versus Efficiency in Parallel Systems≓, IEEE Transactions on Computers, pp. 408–423, Vol. 38, No. 3, March 1989.

    Article  Google Scholar 

  13. European Center for Parallelism of Barcelona (CEPBA), http://www.cepba.upc.es.

  14. D. Feitelson, “Job Scheduling in Multiprogrammed Parallel Systems≓, IBM Research Report 19790, Aug. 1997.

    Google Scholar 

  15. A. Gupta, A. Tucker and S. Urushibara, “The Impact of Operating System Scheduling Policies and Synchronization Methods on the Performance of Parallel Applications≓, ACM SIGMETRICS Performance Evaluation Review, Vol. 19(1), pp. 120–132, May 1991.

    Article  Google Scholar 

  16. J. Heinrich, “MIPS R10000 Microprocessor User’s Manual’, version 2.0, MIPS Technologies, Inc., January 1997.

    Google Scholar 

  17. J. Laudon and D. Lenoski, “The SGI Origin: A ccNUMA Highly Scalable Server≓, Proceedings of the 24th. Annual International Symposium on Computer Architecture, pp. 241–251, Denver, Colorado, June 1997.

    Google Scholar 

  18. S. T. Leutenegger, M. K. Vernon, “The Performance of Multiprogrammed Multiprocessor Scheduling Policies≓, Proceedings of the ACM SIGMETRICS Conference, pp. 226–236, May 22-25, 1990.

    Google Scholar 

  19. B. Marsh, M. Scott, T. LeBlanc and E. Markatos, “First– Class User– Level Threads≓, Proceedings of the 13th. ACM Symposium on Operating System Principles (SOSP), October 1991.

    Google Scholar 

  20. X. Martorell, J. Labarta, N. Navarro and E. Ayguadé, “Nano-Threads Library Design, Implementation and Evaluation≓, Technical Report, Universitat Politècnica de Catalunya, UPC-DAC-1995-33, Sep. 1995.

    Google Scholar 

  21. X. Martorell, J. Labarta, N. Navarro and E. Ayguadé, “A Library Implementation of the Nano– Threads Programming Model≓, Proceedings of the 2nd. Euro– Par Conference, Lyon, France, August. 1996.

    Google Scholar 

  22. C. McCann, R. Vaswani, J. Zahorjan, “A Dynamic Processor Allocation Policy for Multiprogrammed Shared– Memory Multiprocessors≓, ACM Transactions on Computer Systems, 11(2), pp. 146–178, May 1993.

    Article  Google Scholar 

  23. V. K. Naik, S. K. Setia, M. S. Squillante, “Performance Analysis of Job Scheduling Policies in Parallel Supercomputing Environments≓, Proceedings of the Supercomputing ’93, 1993.

    Google Scholar 

  24. V. K. Naik, M. S. Squillante, “Analysis of Cache E.ects and Resource Scheduling in Distributed Parallel Processing Systems≓, Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, SIAM Press, 1995.

    Google Scholar 

  25. T.D. Nguyen, R. Vaswani, J. Zahorjan, “Using Runtime Measured Workload Characteristics in Parallel Processor Scheduling≓, Proc. of the workshop on Job Scheduling Strategies for Parallel Processing, Lecture Notes in Computer Science, vol. 1162, Springer– Verlag, 1996.

    Google Scholar 

  26. OpenMP Architecture Review Board, “Fortran Language Speci.cation, v 1.0≓, http://www.openmp.org/openmp/mp-documents/fspec.ps, October 1997.

  27. J.K. Ousterhout, “Scheduling Techniques for Concurrent Systems≓, Proceedings of the 3rd. International Conference on Distributed Computing and Systems, pp.22–30, 1982.

    Google Scholar 

  28. V. Pillet, J. Labarta, T. Cortés, S. Girona, “PARAVER: A Tool to Visualize and Analyse Parallel Code≓, WoTUG-18, pp. 17–31, Manchester, April 1995. Also as Technical Report UPC-CEPBA-95-03.

    Google Scholar 

  29. E.D. Polychronopoulos, X. Martorell, D. Nikolopoulos, J. Labarta, T. S. Papatheodorou and N. Navarro, “Kernel– level Scheduling for the Nano-Threads Programming Model≓, Proceedings of the 12th ACM International Conference on Supercomputing (ICS’98), Melbourne, Australia, July 1998.

    Google Scholar 

  30. E.D. Polychronopoulos, D.S. Nikolopoulos, T.S. Papatheodorou, X. Martorell, J. Labarta, N. Navarro, “An E.cient Kernel-Level Scheduling Methodology for Multiprogrammed Shared Memory Multiprocessors≓, Proceedings of the 12th International Conference on Parallel and Distributed Computing Systems (PDCS’99), Fort Lauderdale (Florida-USA), August 18-20, 1999.

    Google Scholar 

  31. E.D. Polychronopoulos, D. Nikolopoulos, T. Papatheodorou, X. Martorell, N. Navarro and J. Labarta, “TSDSS – An E.cient and E.ective Kernel– Level Scheduling Methodology for Shared– Memory Multiprocessors≓, Technical Report HPISL-010399, High Performance Information Systems Laboratory, University of Patras, 1999.

    Google Scholar 

  32. C. Severance, R. Enbody, “Automatic Self– Allocating Threads (ASAT) on an SGI Challenge≓, Proc. of the International Conference on Parallel Processing (ICPP96), Vol.3, pp. 132–139, August 1996.

    Google Scholar 

  33. Silicon Graphics Computer Systems SGI, “Origin 200 and Origin 2000 Technical Report≓, 1996.

    Google Scholar 

  34. Silicon Graphics Computer Systems (SGI), “IRIX 6.4/6.5 manual pages: mp(3F) & mp(3C)≓e, IRIX online manuals, also in http://techpubs.sgi.com, 1997-1999.

  35. SPEC Organization, “The Standard Performance Evaluation Corporation≓,http://www.spec.org.

  36. M. S. Squillante, R. D. Nelson, “Analysis of Task Migration in Shared– Memory Multiprocessor Scheduling≓, ACM SIGMETRICS Performance Evaluation Review, vol. 19, no. 1, 1991.

    Google Scholar 

  37. J. Torrellas, A. Tucker, A. Gupta, “Evaluating the Performance of Cache– Affinity Scheduling in Shared– Memory Multiprocessors≓, Journal on Parallel and Distributed Computing, 24(2), pp. 139–151, February 1995.

    Article  Google Scholar 

  38. A. Tucker and A. Gupta, “Process Control and Scheduling Issues for Multiprogrammed Shared– Memory Multiprocessors≓, Proceedings of the 12th. ACM Symposium on Operating System Principles (SOSP), December 1989.

    Google Scholar 

  39. A. Tucker, “Efficient Scheduling on Multiprogrammed Shared– Memory Multiprocessors≓, Ph.D. Thesis, Stanford University, December 1993.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. European Center for Parallelism of Barcelona Departament d’Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain

    Xavier Martorell, Julita Corbalán, Nacho Navarro & JesÚs Labarta

  2. HighP erformance Information Systems Laboratory Department of Computer Engineering And Informatics, University of Patras, Greece

    Dimitrios S. Nikolopoulos, Eleftherios D. Polychronopoulos & Theodore S.

Authors
  1. Xavier Martorell
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Julita Corbalán
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Dimitrios S. Nikolopoulos
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Nacho Navarro
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Eleftherios D. Polychronopoulos
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Theodore S.
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. JesÚs Labarta
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. The Hebrew University School of Computer Science and Engineering, 91904, Jerusalem, Israel

    Dror G. Feitelson

  2. Massachusetts Institute of Technology Laboratory for Computer Science, Cambridge, MA, 02139, USA

    Larry Rudolph

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Martorell, X. et al. (2000). A Tool to Schedule Parallel Applications on Multiprocessors: The NANOS CPU Manager . In: Feitelson, D.G., Rudolph, L. (eds) Job Scheduling Strategies for Parallel Processing. JSSPP 2000. Lecture Notes in Computer Science, vol 1911. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39997-6_7

Download citation

  • DOI: https://doi.org/10.1007/3-540-39997-6_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41120-8

  • Online ISBN: 978-3-540-39997-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation