The work reported here was performed at Syracuse University and was supported by the Air Force Rome Air Development Center under Contract F30602-72-C-0281.
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References
J. C. Hoffmann, B. Lacaze, P. Csillag, "Multiplieur Parallels or Circuits Logiques Iteratiffs", Electronic Letters, vol. 4, No. 9, pp. 178, April 1968.
T. Feng, "Data Manipulating Functions in Parallel Processors and Their Implementation", IEEE Transactions on Computers, vol. C-23, No. 3, pp. 309–318, March 1974.
T. Feng, C. P. Hsu, "Design and Analysis of A Parallel Arithmetic Unit", Technical Report, TR-73-13, Dept. of Electrical and Computer Engineering, Syracuse University, (December 1973).
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Hsu, C.P., Feng, TY. (1975). A reconfigurable parallel arithmetic unit. In: Feng, Ty. (eds) Parallel Processing. SCC 1974. Lecture Notes in Computer Science, vol 24. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-07135-0_135
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DOI: https://doi.org/10.1007/3-540-07135-0_135
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