Abstract
Statistical SPICE modeling is necessary for low risk IC design. Here existing approaches to statistical modeling are reviewed, and their limitations are discussed. A four level hierarchy of IC manufacturing variations is presented. Using physically based process and geometry level modeling, sensitivity analysis, and propagation of variance, it is shown how statistical models can be accurately and efficiently derived from the statistical distributions of key device electrical performances, as measured on manufacturing lines. The procedure runs in minutes of am engineering workstation, and guarantees accurate modeling of manufacturing variations.
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© 2004 Kluwer Academic Publishers
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McAndrew, C.C. (2004). Efficient Statistical Modeling for Circuit Simulation. In: Reis, R., Jess, J.A.G. (eds) Design of System on a Chip. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7929-X_4
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DOI: https://doi.org/10.1007/1-4020-7929-X_4
Publisher Name: Springer, Boston, MA
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