This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
S. Thompson and et al. “A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 mm2 SRAM Cell,” Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp 61–64.
S. E. Thompson and et al., “A Logic Nanotechnology Featuring Strained Silicon,” IEEE Electron Device Letter, vol. 25, pp. 191–193, 2004.
P. Bai, “A 65nm Logic Technology Featuring 35nm Gate Lenghts, Enhanced Channel Strain, 8 cu interconnects Layesrs, Low-k ILD and 0.57um2 SRAM Cell,” Technical Digest of the IEEE International Electron Devices Meeting, vol. pp., 2004.
Z. Ren, M. V. Fischetti, E. P. Gusev, E. A. Cartier, and M. Chudzik, “Inversion channel mobility in high-[kappa] high performance MOSFETs,” Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp 33.2.1–4.
D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley, and R. Chau, “High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics,” International Electron Devices Meeting. Technical Digest, pp. 10.6.1–4, 2001.
D. Kahng and M. M. Atalla. Silicon-silicon dioxide field induced surface devices. IRE-AIEE Solid-State Device Research Conference, Carnegie Institute of Technology, Pittsburgh, PA, 1960.
M. M. Atalla, M. Tannenbaum and E. J. Scheibner, “Stabilization of silicon surface by thermally grown oxides,” Bell Syst. Tech. J., vol. 38, pp. 123, 1959.
E. H. Snow, B. E. Deal, A. S. Grove and C.-T. Sah, “Ion transport phenomena in insulating films using the MOS structure,” J. Appl. Phys., vol. 36, pp. 1664–1673, 1965.
P. Balk, “Effects of hydrogen annealing on silicon surfaces,” Electrochemical Society Spring Meeting, San Francisco, CA, 1965.
B. Doyle, R. Arghavani, D. Barlage, S. Datta, S. Doczy, J. Kavalieros, A. Murthy and R. Chau, “Transistor elements for 30nm physical gate lengths and beyond,” Intel Technology Journal, vol. pp., 2002.
T. Ghani, et. al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp 978–980.
Y. Bin, C. Leland, S. Ahmed, W. Haihong, S. Bell, Y. Chih-Yuh, C. Tabery, H. Chau, X. Qi, K. Tsu-Jae, J. Bokor, H. Chenming, L. Ming-Ren and D. Kyser, “FinFET scaling to 10 nm gate length,” International Electron Devices Meeting. Technical Digest, pp. 251–254, 2002.
R. Chau, B. Boyanov, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros and M. Metz, “Silicon nano-transistors for logic applications,” Physica E: Low-dimensional Systems and Nanostructures, vol. 19, pp. 1–5, 2003.
B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios and a. Chau et, “High performance fully-depleted tri-gate CMOS transistors,” IEEE Electron Device Letters, vol. 24, pp. 263–265, 2003.
R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds and a. Doczy et, “A 50 nm depleted-substrate CMOS transistor (DST),” International Electron Devices Meeting. Technical Digest, pp. 29.1.1–4, 2001.
R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy and a. Dewey et, “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” International Electron Devices Meeting 2000, pp. 45–48, 2000.
J. G. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An and B. Yu, “Physical insights on design and modeling of nanoscale FinFETs,” International Electron Devices Meeting, pp. 679–682, 2003.
V. P. Trivedi and J. G. Fossum, “Scaling fully depleted SOI CMOS,” IEEE Trans. Electron Devices, vol. 50, pp. 2095–2103, 2003.
A. Ural, L. Yiming and D. Hongjie, “Electric-field-aligned growth of single-walled carbon nanotubes on surfaces,” Applied Physics Letters, vol. 81, pp. 3464–3466, 2002.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer Science+Business Media, Inc.
About this chapter
Cite this chapter
Suthram, S., Narendra, S., Thompson, S. (2006). Transistor Design to Reduce Leakage. In: Leakage in Nanometer CMOS Technologies. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28133-9_12
Download citation
DOI: https://doi.org/10.1007/0-387-28133-9_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-25737-2
Online ISBN: 978-0-387-28133-9
eBook Packages: EngineeringEngineering (R0)