Abstract
A fully integrated 0.18μm CMOS ΣΔ fractional synthesizer targeting 3G wireless terminals applications is presented. This work is a practical example of a more general study on frequency fractional synthesis. A simple linear model of the system is presented and used to simulate different ΣΔ modulators topologies and to evaluate the effects of circuits non-idealities particularly on output spurious tones. Phase Frequency Detector (PFD) and Charge Pump (CP) non-linearity effects are analysed in details, the obtained results are confirmed by measurement. Solutions to overcome these limitations are given. At last, a ΣΔ quantization noise compensation technique is presented allowing to break the trade-off between Phase Locked Loop (PLL) bandwidth and high frequency noise regrowth.
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© 2003 Kluwer Academic Publishers
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Bietti, I., Albasini, G., Temporiti, E., Castello, R. (2003). A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser With 35Hz Frequency Step and Quantization Noise Compensation. In: van Roermund, A., Steyaert, M., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48707-1_4
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DOI: https://doi.org/10.1007/0-306-48707-1_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7559-9
Online ISBN: 978-0-306-48707-1
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