Abstract
Realization of the electrical-physical layer for the USB 2.0 standard requires sophisticated mixed-signal electronics. The combination of the new 480 Mb/s high-speed mode together with backward compatibility with USB 1.1 is technically challenging. In this paper the essential parts of the USB protocol are described and important system trade-offs are discussed. Furthermore, the structure and operation of the PHY are explained and implementations of some critical building blocks are shown. The use of integrated calibrated resistors in order to minimize the number of external components is described. Finally, silicon realizations are shown and measured results are presented.
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References
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© 2003 Kluwer Academic Publishers
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den Besten, G.W. (2003). The USB 2.0 Physical Layer: Standard and Implementation. In: van Roermund, A., Steyaert, M., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48707-1_17
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DOI: https://doi.org/10.1007/0-306-48707-1_17
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7559-9
Online ISBN: 978-0-306-48707-1
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