Advertisement

Digital implementation of artificial neural networks: From VHDL description to FPGA implementation

  • N. Izeboudjen
  • A. Farah
  • S. Titri
  • H. Boumeridja
Artificial Neural Nets Simulation and Implementation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1607)

Abstract

This paper deals with a top down design methodology of an artificial neural network (ANN) based upon parametric VHDL description of the network. To come off early in the design process a high regular architecture was achieved. Then, the VHDL parametric description of the network was realized. The description has the advantage of being generic, flexible and can be easily changed at the user demand. To validate our approach, an ANN for electrocardiogram (ECG) arrhythmia's classification is passed through a synthesis tool, GALILEO, for FPGA implementation.

Key words

ANN top down design VHDL parametric description FPGA implementation 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    M. I. Elmasry, «VLSI Artificial Neural Networks Engineering», Kluwer Academic Publshers.Google Scholar
  2. [2]
    Richard P. Lippmann, «An Introduction to computing with Neural Nets», IEEE ASSP Magazine, pp. 4–22. April 1987.Google Scholar
  3. [3]
    Philip Trealeven, Macro Pacheco and Marley Vellasco, «VLSI Architectures for Neural Networks», IEEE MICRO, pp. 8–27, December 1989.Google Scholar
  4. [4]
    Y. Arima, K. Mashiko, K. Okada, «A Self-Learning Neural Network Chip with 125 Neurons and 10K Self-Ornization Synapses», Symposium on VLSI Circuits, pp. 63–64, 1990 IEEE.Google Scholar
  5. [5]
    H. Ossoing, «Design and FPGA-Implementation of Neural Network», ICSPAT'96, Pp. 939–943.Google Scholar
  6. [6]
    Charles E. Cox and W. Ekkehard Blanz, «GANGLION—A Fast Field Programmable Gate Array Implementation of a Connectionist Classifier», IEEE JSSC, Vol. 27, No. 3, pp. 288–299, March 1992.Google Scholar
  7. [7]
    R. Airiau, J. M. Berge, V. Olive, J. Rouillard “VHDL du language a la modelisation”, Presses Polytechniques et Universitaires Romandes et CNEST-ENST.Google Scholar
  8. [8]
    R. Airiau, J. M. Berge, V. Olive, “Circuit Synthesis with VHDL”, Kluwer Academic Publishers.Google Scholar
  9. [9]
    Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin, “High level Synthesis-Introduction to Chip and System Design”, Kluwer Academic Publishers.Google Scholar
  10. [10]
    XACT user manual.Google Scholar
  11. [11]
    M. S. Ben Romdhane, V. K. Madissetti and J. W. Hines, “Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis”, Kluwer Academic Publishers.Google Scholar
  12. [12]
    N. Izeboudjen and A. Farah, “A New Neural Network System for arrhythmia's Classification,” NC'98, International ICSC/IFAC Symposium on neural Computation. Vienna, September 23–25, pp. 208–212.Google Scholar
  13. [13]
    GALILEO HDL Synthesis Manual.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • N. Izeboudjen
    • 1
  • A. Farah
    • 2
  • S. Titri
    • 1
  • H. Boumeridja
    • 1
  1. 1.Microelectronic LaboratoryDevelopment Center of Advanced TechnologiesAlgiers-Algeria
  2. 2.Laboratoire Techniques Digitales et SystemesEcole Nationale PolytechniqueAlgiers-Algeria

Personalised recommendations