Digital implementation of artificial neural networks: From VHDL description to FPGA implementation

  • N. Izeboudjen
  • A. Farah
  • S. Titri
  • H. Boumeridja
Artificial Neural Nets Simulation and Implementation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1607)


This paper deals with a top down design methodology of an artificial neural network (ANN) based upon parametric VHDL description of the network. To come off early in the design process a high regular architecture was achieved. Then, the VHDL parametric description of the network was realized. The description has the advantage of being generic, flexible and can be easily changed at the user demand. To validate our approach, an ANN for electrocardiogram (ECG) arrhythmia's classification is passed through a synthesis tool, GALILEO, for FPGA implementation.

Key words

ANN top down design VHDL parametric description FPGA implementation 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • N. Izeboudjen
    • 1
  • A. Farah
    • 2
  • S. Titri
    • 1
  • H. Boumeridja
    • 1
  1. 1.Microelectronic LaboratoryDevelopment Center of Advanced TechnologiesAlgiers-Algeria
  2. 2.Laboratoire Techniques Digitales et SystemesEcole Nationale PolytechniqueAlgiers-Algeria

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