Large neural net simulation under Beowulf-like systems

  • Carlos J. García Orellana
  • Francisco J. López
  • Horacio M. González Velasco
  • Miguel Macías Macías
  • M. Isabel Acevedo Sotoca
Artificial Neural Nets Simulation and Implementation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1607)


In this work we broach the problem of large neural network simulation using low-cost distributed systems. We have developed for the purpose high-performance client-server simulation software, where the server runs on a multiprocessor Beowulf system. On the basis of a performance analysis, we propose an estimator for the simulation time.


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  1. 1.
    Agarwal A., Kranz D.A., Natarajan V.: Automatic partitioning of parallel loops and data arrays for distributed shared-memory multiprocessors. IEEE Trans. Parallel Distributed Systems, 6(9):943–962, 1995.CrossRefGoogle Scholar
  2. 2.
    Becker D.J., Sterling T., Savarese D., Dorband J.E., Ranawak U.A., Packer C.V. Beowulf: A Parallel workstation for scientific computation. Proceedings, International Conference on Parallel Processing, 1995.Google Scholar
  3. 3.
    Boulet P., Darte A., Risset T. and Robert Y. (Pen)-ultimate tiling?. Integration, the VLSI Journal, 17:33–51, 1994.CrossRefGoogle Scholar
  4. 4.
    Pierre Boulet, Jack Dongarra, Yves Robert and Frederic Vivien, Tiling for Heterogeneous Computing Platforms, Report UT-CS-97-373, Jul 1997Google Scholar
  5. 5.
    Calland P.Y., Dongarra J. and Robert Y. Tiling with limited resources. Application Specific Systems, Architectures and Processors. ASAP'97, pp 229–238. IEEE Computer Society Press, 1997.Google Scholar
  6. 6.
    Darte A., Khachiyan L. and Robert Y. Linear Scheduling is Nearly Optimal. Parallel Processing Letters, vol 1.2, pp. 73–81, 1991.CrossRefGoogle Scholar
  7. 7.
    Desprez F., Dongarra J., Rastello F. and Robert Y. Determining the Idle Time of a Tiling: New Results Journal of Information Science and Engineering, pp. 167–190, Vol. 14 No. 1. March 1997.Google Scholar
  8. 8.
    García Orellana, C.J. Modelado y Simulación de Grandes Redes Neuronales. Doctoral Thesis—University of Extremadura. October” 1998.Google Scholar
  9. 9.
    Hodzic E. and Shang W. On Supernode Transformation with Minimized Total Running Time. IEEE Transactions on Parallel and Distributed Systems. Vol. 9, No5. May 1998. pp. 417–428CrossRefGoogle Scholar
  10. 10.
    Irigoin F. and Triolet R. Supernode partitioning. In Proc. 15th Annual ACM Symp. Principles of Programming Languages, pages 319–329, CA, January 1988.Google Scholar
  11. 11.
    A. Müller, A. Gunzinger and W. Guggenbühl, Fast Neural Net Simulation with a DSP Processor Array. IEEE Transactions On Neural Networks, Vol. 6, No. 1, January 1995.Google Scholar
  12. 12.
    Ohta H., Saito Y., Kainaga M. and Ono H. Optimal Tile Size Adjustment in Compiling General DOACROSS Loop Nets. Proc. 1995 Int'l Conf. Supercomputing, pp. 270–279. ACM Press, 1995.Google Scholar
  13. 13.
    U. Ramacher et al., SYNAPSE-1—A General Purpose Neurocomputer, Siemens AG, available on request Feb. 1994.Google Scholar
  14. 14.
    Ramanujam J. and Sadayappan P. Tiling Multidimensional Iteration Spaces for Multicomputers. J. Parallel and Distributed Computing, vol. 16, pp. 108–120, 1992.CrossRefGoogle Scholar
  15. 15.
    Reschke C., Sterling, T., Ridge D., Savarese D. Becker, D., Merkey P. A Desing Study of Alternative Network Topologies for the Beowulf Parallel Workstation. Proceedings, High Performance and Distributed Computing, 1996.Google Scholar
  16. 16.
    Schreiber R. y Dongarra J.J. Automatic Blocking of Nested Loops. Technical Report 90.38, RIACS, Aug. 1990.Google Scholar
  17. 17.
    Shang W. and Fortes, J.A.B. Time Optimal Linear Schedules for Algorithms with Uniform Dependencies. IEEE Trans. Computers, vol 40, no 6, pp 723–742, Jun 1991.CrossRefMathSciNetGoogle Scholar
  18. 18.
    Shang W. and Fortes, J.A.B. Independent Parttioning of Algorithms with Uniform Dependencies. IEEE Trans. Computers, vol 41, no 2, pp 190–206, Feb 1992.CrossRefGoogle Scholar
  19. 19.
    Sterling T., Becker D.J., Savarese D., Berry M.R., Reschke C. Achieving a Balanced Low-Cost Architectures for Mass Storage Management through Multiple Fast Ethernet Channels on a Beowulf Parallel Workstation. Proceedings, International Parallel Processing Symposium, 1996.Google Scholar
  20. 20.
    Warren M.S., Salmon J.K., Becker D.J., Goda M.P., Sterling T., Winckelmans G.S.: Pentium Pro inside: I. a treecode at 430 Gigaflops on ASCI Red, II. Price/performance of $50/Mflop on Loki and Hyglac. In Supercomputing'97. Los Alamitos, 1997. IEEE Computer Society.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Carlos J. García Orellana
    • 1
  • Francisco J. López
    • 1
  • Horacio M. González Velasco
    • 1
  • Miguel Macías Macías
    • 1
  • M. Isabel Acevedo Sotoca
    • 1
  1. 1.Departamento de Electrónica e Ing. ElectromecánicaUniversidad de ExtremaduraBadajozSpain

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