Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor
This paper presents the results obtained by a new parallel procedure that generates the patterns for testing digital circuits when it is implemented in a shared-memory multiprocessor. The procedure is based on a new sequential algorithm which mixes both the Boolean difference and digital spectral techniques, thus being different from other parallel methods proposed up to now. First, it uses a static circuit partitioning procedure and later a dynamic load balancing scheme to distribute the load among the processors.
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