Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor

  • Consolación Gil
  • Julio Ortega
  • Jose Luis Bernier
  • Maria Dolores Gil
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1541)


This paper presents the results obtained by a new parallel procedure that generates the patterns for testing digital circuits when it is implemented in a shared-memory multiprocessor. The procedure is based on a new sequential algorithm which mixes both the Boolean difference and digital spectral techniques, thus being different from other parallel methods proposed up to now. First, it uses a static circuit partitioning procedure and later a dynamic load balancing scheme to distribute the load among the processors.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Consolación Gil
    • 1
  • Julio Ortega
    • 2
  • Jose Luis Bernier
    • 2
  • Maria Dolores Gil
    • 1
  1. 1.Dept. de Arquitectura de Computadores y ElectrónicaUniversidad de AlmeráAlmeríaSpain
  2. 2.Dept. de Arquitectura y Tecnología de ComputadoresUniversidad de GranadaGranadaSpain

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