Multithreaded LOGFLOW on KUMP/D
The exploited parallelism offered by logic programming languages is usually categorized, as OR-parallelism and AND-parallelism. Another dimension could be the level of functionality where the parallelism is exploited. In this paper a novel approach is described where the parallelism is utilized at thread level. There are two cornerstones in the project. Implementing a macro dataflow model on a hybrid dataflow/von Neumann multithreaded architecture promises an efficient hardware support. Furthermore, by utilizing the features of a multithreaded architecture, remote memory accesses without significant loss of performance allow a new way of variable handling. Both the MPAM (multithreaded Prolog Abstract Machine) and the physical machine (KUMP/D, where the system is going to be implemented, are presented here.
Keywordsmacro dataflow model multithreading Prolog abstract machine
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- 1.H. Ait-Kaci: Warren's Abstract Machine. MIT Press, 1991.Google Scholar
- 2.M. Amamiya, R. Taniguchi: Datarol: A Massively Parallel Architecture for Functional Language. Proc. Second IEEE Symposium on Parallel and Distributed Processing, 1990, 726–735.Google Scholar
- 3.Arvind and R.A. Ianucci: Two fundamental issues in multiprocessing. Proc. DFVLR Conf. 1987 on Parallel Processing in Science and engineering Bonn-Bad Godesberg, 1987.Google Scholar
- 4.J.S. Conery: Binding Environments for Parallel Logic Programs in Non-Shared Memory Multiprocessors. Proceedings of the 1987 Symp. on Logic Programming. 1987.Google Scholar
- 5.R.A. Ianucci: Towards a dataflow/von Neumann hybrid architecture. Proc. 15th Ann. Int. Symp. on Computer Architecture, May 1988.Google Scholar
- 6.P. Kacsuk: Distributed Data Driven Prolog Abstract Machine. In: P. Kacsuk, M.J. Wise: Implementations of Distributed Prolog. Wiley, 1992.Google Scholar
- 7.P. Kacsuk: Execution, Models for a Massively Parallel Prolog Implementation. Journal of Computers and Artificial Intelligence, Vol. 17, No. 4. Slovak Academy of Sciences, 1998.Google Scholar
- 8.T. Kawano, S. Kusakabe, R. Taniguchi, M. Anamiya: Fine-grain multi-thread processor architecture for massively parallel processing. Proc. First IEEE Symp. High Performance Computer Architecture, 1995.Google Scholar
- 9.Zs. Németh, P. Kacsuk: Analysis and Improvement of the Variable Binding Scheme in LOGFLOW, Workshop on Parallelism and Implementation Technology for (Constraint) Logic Programming, Languages, Port Jefferson, 1997.Google Scholar
- 10.M. Sato, Y. Kodayama, S. Sakai, Y. Yamaguchi, Y. Koumura: Thread-based programming for the EM-4 hybrid dataflow machine. Proc. 19th Ann. Int. Symp. on Computer Architecture, May 1992.Google Scholar
- 11.D. Sima, T. Fountain, P. Kacsuk: Advanced Computer Architectures. Addison Wesley, 1997.Google Scholar
- 12.H. Tomiyasu, T. Kawano, R. Taniguchi, M. Amamiya: KUMP/D: the Kyushu University Multi-media Processor. Proceedings of the Computer Architectures for Machine Perception, CAMP95. pp 367–374.Google Scholar