Profile-based selection of load value and address predictors

  • Toshinori Sato
II System Architecture
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1615)


In this paper, we investigate hybrid predictors for data speculation. In order to increase opportunities for data speculation as well as improve prediction accuracy, we propose to combine a load address predictor with a load value predictor. For each instruction, by choosing the more accurate predictor, we improve prediction accuracy. We investigate two types of hybrid predictors. One has an adaptive mechanism for choosing the more accurate one dynamically, and the other decides the selection statically using execution profiles. The latter one has the benefit that the hardware cost of the selecting mechanism is removed. We have evaluated the predictors using a cycle-by-cycle simulator and found that contribution of the static hybrid predictor to processor performance is comparable to that of the dynamic one.


instruction level parallelism architecture dynamic speculation of data dependence hybrid predictors execution profiles optimizing compilers 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Burger, D., Austin, T.M.: The SimpleScalar tool set, version 2.0 ACM SIGARCH Computer Architecture News, 25 (3) (1997)Google Scholar
  2. 2.
    Calder, B., Feller, P., Eustace, A.: Value profiling. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  3. 3.
    Chen, T-F., Baer, J-L.: Effective hardware-based data prefetching for high-performance processors. IEEE Trans. Comput., 44 (5) (1995)Google Scholar
  4. 4.
    Gabbay, F., Mendelson, A.: Can program profiling support value prediction?. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  5. 5.
    Gonzalez, J., Gonzalez, A.: Speculative execution via address prediction and data prefetching. 11th Int'l Conf. on Supercomputing (1997)Google Scholar
  6. 6.
    Lipasti, M.H., Wilkerson, C.B., Shen, J.P.: Value locality and load value prediction. Int'l Conf. on Architectural Support for Programming Languages and Operating Systems VII (1996)Google Scholar
  7. 7.
    Lipasti, M.H., Shen, J.P.: Exceeding the dataflow limit via value prediction. 29th Int'l Symp. on Microarchitecture (1996)Google Scholar
  8. 8.
    McFarling, S.: Combining branch predictors. WRL Technical Note TN-36, Digital Western Research Laboratory (1993)Google Scholar
  9. 9.
    Moshovos, A.I., Sohi, G.S.: Streamlining inter-operation memory communication via data dependence prediction. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  10. 10.
    Reinman, G., Calder, B.: Predictive techniques for aggressive load speculation. 31st Int'l Symp. on Microarchitecture (1998)Google Scholar
  11. 11.
    Sato, T.: Speculative resolution of ambiguous memory aliasing. In: Veidenbaum, A., Joe, K. (eds): Innovative Architecture for Future Generation High-Performance Processors and Systems, IEEE-CS Press (1998)Google Scholar
  12. 12.
    Sato, T.: Analyzing overhead of reissued instructions on data speculative processors. Workshop on Performance Analysis and its Impact on Design held in conjunction with 25th Int'l Symp. on Computer Architecture (1998)Google Scholar
  13. 13.
    Sato, T.: Load value prediction using two-hop reference address renaming. 4th Int'l Conf. on Computer Science & Informatics (1998)Google Scholar
  14. 14.
    Sato, T.: Reducing miss penalty of load value prediction using load address prediction. In: Morris, J. (ed.): Computer Architecture '99. Australasian Computer Science Communications, 21 (4). Springer-Verlag, Singapore (1999)Google Scholar
  15. 15.
    Sazeides, Y., Vassiliadis, S., Smith, J.E.: The performance potential of data dependence speculation & collapsing. 29th Int'l Symp. on Microarchitecture (1996)Google Scholar
  16. 16.
    Sazeides, Y., Smith, J.E.: The predictability of data value. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  17. 17.
    Sohi, G.S.: Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Trans. Comput., 39 (3), (1990)Google Scholar
  18. 18.
    Tyson, G., Austin, T.M.: Improving the accuracy and performance of memory communication through renaming. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  19. 19.
    Wang, K. Franklin, M.: Highly accurate data value prediction using hybrid predictors. 30th Int'l Symp. on Microarchitecture (1997)Google Scholar
  20. 20.
    Widigen, L., Sowadsky, E., McGrath, K.: Eliminating operand read latency. ACM SIGARCH Computer Architecture News, 24 (5) (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Toshinori Sato
    • 1
  1. 1.Toshiba Microelectronics Engineering LaboratoryKawasakiJapan

Personalised recommendations