Evaluating ASIC, DSP, and RISC architectures for embedded applications

  • Marc Campbell
Refereed Papers Invited Talks
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1474)


Mathematical analysis and empirical evaluation, based on solid state physical behavior, identifies a Architecture-Technology Metric for measuring the relative specialization of ASIC, DSP, and RISC architectures for embedded applications. Relationships are examined which can help predict relative future architecture performance as new generations of CMOS solid state technology become available. In particular, Performance/Watt is shown to be an Architecture-Technology Metric which can be used to calibrate ASIC, DSP, & RISC performance density potential relative to a solid state technology generations, measure & evaluate architectural changes, and project a architecture performance density roadmap.


  1. 1.
    Campbell, M. E.: Evaluating ASIC, DSP, and RISC Architectures for Applications. In Proceedings of the 12th Int. Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, pages 600–603, IEEE, 1998.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Marc Campbell
    • 1
  1. 1.Northrop Grumman CorporationUSA

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