A complete and constant time wait-free implementation of CAS from LL/SC and vice versa

  • Prasad Jayanti
Contributed Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1499)


We consider three popular types of shared memory that support one of the following sets of operations: {CAS, read, write}, {LL, SC, VL, read, write}, or {RLL, RSC, read, write}. We present algorithms that, together with Moir's [Moi97], efficiently implement each shared memory above from any of the other two. Our implementations are wait-free and have constant time and space complexity. Thus, concurrent programs developed for one of the above memories can be ported to any other without incurring any increase in time complexity. Further, since our implementations are wait-free, a wait-free concurrent program remains wait-free even after porting.

This work is similar in spirit to [IR94, AM95, Moi97]. The main difference is that in these earlier works the write operation is not included in the set of implemented operations. Specifically, earlier works implement {CAS, read} from {LL, SC} and vice versa, but to our knowledge there are no existing implementations of either of {CAS, read, write} and {LL, SC, VL, read, write} from the other. Consequently, it is not possible to port concurrent programs between systems supporting {CAS, read, write} and {LL, SC, VL, read, write}. The implementations in this paper help overcome this drawback.

At first glance, adding write to the set of implemented operations might appear easy. However, there is ample evidence to suggest that simple modifications to earlier implementations do not work. Our implementations are therefore quite different from the ones in earlier works.


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  1. [AM95]
    J. Anderson and M. Moir. Universal constructions for multi-object operations. In Proceedings of the 14th Annual ACM Symposium on Principles of Distributed Computing, pages 184–194, August 1995.Google Scholar
  2. [Her91]
    M.P. Herlihy. Wait-free synchronization. ACM TOPLAS, 13(1):124–149, 1991.CrossRefGoogle Scholar
  3. [HS93]
    M. P. Herlihy and N. Shavit. The asynchronous computability theorem for t-resilient tasks. In Proceedings of the 25th ACM Symposium on Theory of Computing, pages 111–120, 1993.Google Scholar
  4. [HW90]
    M.P. Herlihy and J.M. Wing. Linearizability: A correctness condition for concurrent objects. ACM TOPLAS, 12(3):463–492, 1990.CrossRefGoogle Scholar
  5. [IBM94]
    IBM. The Power PC Architecture: A specification for a new family of RISC processors. Morgan-Kaufmann, 1994.Google Scholar
  6. [IR94]
    A. Israeli and L. Rappoport. Disjoint-Access-Parallel implementations of strong shared-memory primitives. In Proceedings of the 13th Annual ACM Symposium on Principles of Distributed Computing, pages 151–160, August 1994.Google Scholar
  7. [Jay98]
    P. Jayanti, 1998. See Scholar
  8. [JHB87]
    E. Jensen, G. Hagensen, and J. Broughton. A new approach to exclusive data access in shared-memory multiprocessors. Technical Report Technical Report UCRL-97663, Lawrence Livermore National Laboratory, 1987.Google Scholar
  9. [Kan89]
    G. Kane. MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs, N.J., 1989.Google Scholar
  10. [Lam77]
    L. Lamport. Concurrent reading and writing. Communications of the ACM, 20(11):806–811, 1977.MATHMathSciNetCrossRefGoogle Scholar
  11. [Moi97]
    M. Moir. Practical implementations of non-blocking synchronization primitives. In Proceedings of the 16th Annual ACM Symposium on Principles of Distributed Computing, pages 219–228, August 1997.Google Scholar
  12. [Sit92]
    R. Site. Alpha Architecture Reference Manual. Digital Equipment Corporation, 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Prasad Jayanti
    • 1
  1. 1.Dartmouth CollegeHanoverUSA

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