On discretization of delays in timed automata and digital circuits

  • Eugene Asarin
  • Oded Maler
  • Amir Pnueli
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1466)


In this paper we solve the following problem: “given a digital circuit composed of gates whose real-valued delays are in an integer-bounded interval, is there a way to discretize time while preserving the qualitative behavior of the circuit?” This problem is described as open in [BS94]. When “preservation of qualitative behavior” is interpreted in a strict sense, as having all original sequences of events with their original ordering we obtain the following two results:
  1. 1)

    For acyclic (combinatorial) circuits whose inputs change only once, the answer is positive: there is a constant δ, depending on the maximal number of possible events in the circuit, such that if we restrict all events to take place at multiples of δ, we still preserve qualitative behaviors.

  2. 2)

    For cyclic circuits the answer is negative: a simple circuit with three gates can demonstrate a qualitative behavior which cannot be captured by any discretization.


Nevertheless we show that a weaker notion of preservation, similar to that of [HMP92], allows in many cases to verify discretized circuits with δ=1 such that the verification results are valid in dense time.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [ACD93]
    R. Alur, C. Courcoubetis, and D.L. Dill, Model Checking in Dense Real Time, Information and Computation 104, 2–34, 1993.MATHMathSciNetCrossRefGoogle Scholar
  2. [AD94]
    R. Alur and D.L. Dill. A theory of timed automata, Theoretical Computer Science, 126, 183–235, 1994.MATHMathSciNetCrossRefGoogle Scholar
  3. [ABK+97]
    E. Asarin, M. Bozga, A. Kerbrat, O. Maler, A. Pnueli and A. Rasse, Data-Structures for the Verification of Timed Automata, in O. Maler (Ed.), Proc. HART'97, LNCS 1201, 346–360, Springer, 1997.Google Scholar
  4. [BM98]
    M. Bozga and O. Maler, Modeling and Verification of the STARI Chip using Timed Automata, submitted, 1998.Google Scholar
  5. [BMPY97]
    M. Bozga, O. Maler, A. Pnueli and S. Yovine, Some Progress in the Symbolic Verification of Timed Automata, in O. Grumberg (Ed.) Proc. CAV'97, 179–190, LNCS 1254, Springer, 1997.Google Scholar
  6. [BS94]
    J.A. Brzozowski and C-J.H. Seger, Asynchronous Circuits, Springer, 1994.Google Scholar
  7. [DOTY96]
    C. Daws, A. Olivero, S. Tripakis, and S. Yovine, The Tool KRONOS, in R. Alur, T.A. Henzinger and E. Sontag (Eds.), Hybrid Systems III, LNCS 1066, 208–219, Springer, 1996.Google Scholar
  8. [D89]
    D.L. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in J. Sifakis (Ed.), Automatic Verification Methods for Finite State Systems, LNCS 407, 197–212, Springer, 1989.Google Scholar
  9. [HNSY94]
    T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine, Symbolic Model-checking for Real-time Systems, Information and Computation 111, 193–244, 1994.MATHMathSciNetCrossRefGoogle Scholar
  10. [L90]
    H.R. Lewis, A logic of concrete time intevrals, Proc. LICS'90, IEEE, 1990.Google Scholar
  11. [GPV94]
    A. Göllü, A. Puri and P. Varaiya, Discretization of Timed Automata, Proc. 33rd CDC, 1994.Google Scholar
  12. [HMP92]
    T. Henzinger, Z. Manna, and A. Pnueli. What Good are Digital Clocks?, in W. Kuich (Ed.), Proc. ICALP'92, LNCS 623, 545–558, Springer, 1992.Google Scholar
  13. [MP95]
    O. Maler and A. Pnueli, Timing Analysis of Asynchronous Circuits using Timed Automata, in P.E. Camurati, H. Eveking (Eds.), Proc. CHARME'95, LNCS 987, 189–205, Springer, 1995.Google Scholar
  14. [MY96]
    O. Maler and S. Yovine, Hardware Timing Verification using KRONOS, In Proc. 7th Israeli Conference on Computer Systems and Software Engineering, Herzliya, Israel, June 1996.Google Scholar
  15. [RT97]
    A. Rabinovich and B.A. Trakhtenbrot, From finite automata toward hybrid systems, Proc. FCT'97, 1997.Google Scholar
  16. [TB97]
    S. Tasiran and R.K. Brayton, STARI: A Case Study in Compositional and Hierarchical Timing Verification, in O. Grumberg (Ed.) Proc. CAV'97, 191–201, LNCS 1254, Springer, 1997.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Eugene Asarin
    • 1
  • Oded Maler
    • 2
  • Amir Pnueli
    • 3
  1. 1.Institute for Information Transmission ProblemsMoscowRussia
  2. 2.VerimagCentre EquationGièresFrance
  3. 3.Dept. of Computer ScienceWeizmann Inst.RehovotIsrael

Personalised recommendations