Fair synchronous transition systems and their liveness proofs

  • A. Pnueli
  • N. Shankar
  • E. Singerman
Selected Presentations Verification
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1486)


We present a compositional semantics of synchronous systems that captures both safety and progress properties of such systems. The fair synchronous transitions systems (Fsts) model we introduce in this paper extends the basic αSts model [KP96] by introducing operations for parallel composition, for the restriction of variables, and by addressing fairness. We introduce a weak fairness (justice) condition which ensures that any communication deadlock in a system can only occur through the need for external synchronization. We present an extended version of linear time temporal logic (Eltl) for expressing and proving safety and liveness properties of synchronous specifications, and provide a sound and compositional proof system for it.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • A. Pnueli
    • 1
  • N. Shankar
    • 2
  • E. Singerman
    • 2
  1. 1.Weizmann Institute of ScienceRehovotIsrael
  2. 2.SRI InternationalMenlo ParkUSA

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