The >S<puter: Introducing a novel concept for dispatching instructions using reconfigurable hardware
A novel model for executing programs inside microprocessors is introduced, based on the integration of programmable structures in the dispatch and execution unit. These structures enable the highest degree of instruction parallelism while maintaining the strong sequence of results. The new model is introduced but not limited to register-based processors, while the requested compiler technology proves to be the same as for superscalar processors.
KeywordsBasic Block Register Transfer Level Arithmetic Unit Execution Unit Reconfigurable Hardware
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