The PLD-implementation of Boolean function characterized by minimum delay

  • Valeri Tomachev
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


Let a Boolean function be represented by the SOP (sum-of-products) which involves q products. Let there be only p, there p<q, product terms per combinatorial macrocell of given PLDs. It is shown how to implement that SOP as a one-level logic circuit characterized by minimum delay. The main idea is to use the dynamic output enable control tools for switching the combinatorial macrocells of PLDs. The output enable product terms are chosen so that only one of them is true at every instant. To find these product terms the SOP of Boolean function is converted by factorization into the next form SOP=k1(SOP1)v...vkr(SOPr). Every SOPi, is chosen so that it can be implemented by single combinatorial macrocell. The factor-products k1,...,kr are ortho to each other, and k1v...vk1≡1. The factor-product ki is used for output enable/disable control of the macrocell where SOPi is implemented.


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  1. 1.
    PAL® Device Data Book and Design Guide. Advanced Micro Devices (1995)Google Scholar
  2. 2.
    Tomachev, V.F.: The Minimization of the Delay in the PAL-Implementation of Boolean Function. In: Zakrevskij, A.D. (ed.): Logical Design, Vol.2. Institute of Engineering Cybernetics of NAS of Belarus, Minsk (1997) 52–58 (in Russian)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Valeri Tomachev
    • 1
  1. 1.Logical Design LaboratoryInstitute of Engineering CyberneticsMinskBelarus

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