XILINX4000 architecture — Driven synthesis for speed
Architecture-driven (instead of LUT-driven) method of boolean functions logic synthesis for speed is proposed. It takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each node can be mapped onto 4 input LUT). In the second step, selected 4 fanin nodes within a critical path are re-decomposed into 3 fanin nodes to ensure mapping onto 3 input LUTs. Re-decomposition task is formulated as substituting node two fanins for exactly one fanin. Either existing node or one especially created, is considered as a fanin to be substituted for. The extended PLA format describing a multi-level boolean network, is proposed. Based on this description, substituting is formulated in terms of a covering task.
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