Maestro-link: A high performance interconnect for PC cluster
Maestro is a distributed shared memory system currently being developed. In this paper, an architecture of the high performance network interface of Maestro is presented. Maestro consists of multiple PC(Personal Computers and dedicated network hardware for high performance message passing and maintaining cache coherency. IEEE1394, a high performance serial link, is used in the physical layer of Maestro network. The network interface is developed using FPGA(Field Programmable Gate Array)s. A network latency and a bandwidth between the network interface and PC are measured and discussed.
Unable to display preview. Download preview PDF.
- K. Li, IVY: A Shared Virtual Memory System for Parallel Computing, Proc. of the 1988 Intl Conf. on Parallel Processing (ICPP'88), Vol. II,pp. 94–101, Aug 1988.Google Scholar
- J. Kuskin etal, The Stanford FLASH Multiprocessor, Proc. of the 21th Annual Int'l Symp. on Computer Architecture (ISCA'94), pp. 302–313,Apr 1994.Google Scholar
- C. Amza and A. L. Cox and S. Dwarkadas and P. Keleher and H. Lu and R. Rajamony and W. Yu and W. Zwaenepoel, TreadMarks: Shared Memory Computing on Networks of Workstations, IEEE Computer, Vol. 29, Number 2, pp. 18–28, Feb 1996.Google Scholar
- J. P. Singh and T. Joe and A. Gupta and J. L. Hennessy, An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford DASH Multiprocessors, Proc. of Supercomputing'93, pp. 214–225,Nov 1994.Google Scholar
- IEEE Standard Department, IEEE Standard for a High Performance Serial Bus Draft7.1v1, August 5, 1994.Google Scholar
- Altera Corporation, 1996 Data Book, 1996Google Scholar
- PLX Technology, PCI9060 Data Sheet VERSION1.2, December 1995.Google Scholar